Senior IC Design Verification Application Engineer

About the role

We offer amazing opportunities to grow, no matter where you are in your career. The ideal candidate will be energetic, innovative and enthusiastic about how to help customers solve their toughest verification problems using Cadence technology. Join our elite application engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces™ year after year!

Responsibilities

• Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support
• In collaboration with R&D, provide in-depth technical assistance to help support advanced verification flows and AI/ML applications to secure design wins
• Champion the customer needs and work closely with R&D and marketing to develop competitive and creative technical solutions
• Understand the competitive landscape and continuously work on differentiating Cadence’s solutions
• Write technical product literature such as application notes and technical articles
• Review new product proposals and device specifications
• Assume technical leadership roles in small teams as needed

Requirements

• Minimum: BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field
• 7+ years experience with SystemVerilog, VHDL, Verilog Verification skills such as UVM testbench architecture, development and debug
• Strong RTL and Testbench debug skills
• Experience in writing scripts (Perl, Python or Tcl)
• Strong software, HDL design and verification skills
• Ability to quickly analyze verification environments and design complexity
• Strong verbal and written communication skills
• Strong teamwork skills
• Ability to interact effectively with both external customers and R&D teams

Preferred Experience

• With C/C++/SystemC
• Experience in deploying VIP in testbenches
• Knowledge of protocols like JTAG, UART, PCIe, AMBA, DDR
• Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing
• Digital design experience

Pay

The annual salary range for California is $84,000 to $156,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.

Schedule

Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.