Senior FPGA Compiler (Router) Engineer

Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are at the core of enabling customers to efficiently map complex designs to cutting-edge FPGA architectures.

About the role

Altera is seeking a Senior FPGA Compiler Engineer (Routing) to join our team! This role focuses on the development and optimization of FPGA routing algorithms within the compiler toolchain, directly impacting performance, power, and usability of next-generation FPGA devices. The ideal candidate brings strong expertise in EDA algorithms, graph-based optimization, and FPGA/ASIC design flows, along with a passion for solving complex problems at scale.

Responsibilities

• Routing Algorithm Development: Design, implement, and optimize FPGA routing algorithms to improve performance, routability, and timing closure.
• Compiler Enhancement: Contribute to the FPGA compiler flow, including placement, routing, and timing-driven optimization.
• Performance Optimization: Analyze and improve runtime, memory efficiency, and scalability of routing algorithms for large designs.
• Cross-Functional Collaboration: Work closely with architecture, synthesis, timing (STA), and hardware teams to align routing strategies with device capabilities.
• Debug & Analysis: Investigate routing congestion, timing violations, and design bottlenecks; develop solutions to improve convergence.
• Toolchain Integration: Integrate routing features into existing compiler infrastructure and ensure robustness across diverse customer use cases.

Requirements

• 9+ years of experience in FPGA/ASIC design tools, EDA, or related fields.
• Strong background in algorithms and data structures (graph algorithms, optimization techniques).
• Experience with FPGA or ASIC design flows (placement, routing, timing closure).
• Proficiency in C/C++ and software development best practices.
• Familiarity with routing algorithms (e.g., maze routing, negotiated congestion).
• Understanding of timing-driven design methodologies and physical design concepts.
• Ability to analyze complex systems and develop scalable, high-performance solutions.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Strong communication, teamwork, and interpersonal skills.

Preferred Qualifications

• Experience with commercial FPGA toolchains (e.g., Quartus, Vivado).
• Knowledge of FPGA architectures and interconnect fabrics.
• Familiarity with parallel/distributed computing for EDA workloads.
• Experience with scripting (Python, Tcl) for tooling and automation.
• Background in timing analysis or placement algorithms.

Benefits

• Work on core compiler technology that powers next-generation FPGA platforms.
• Solve complex algorithmic challenges at scale.
• Collaborate with world-class teams across architecture, silicon, and software.

Pay

The pay range below is for Bay Area California only. Actual salary may vary based on job location, job-related knowledge, skills, experiences, and trainings. We also offer incentive opportunities that reward employees based on individual and company performance.

$187,000 - $270,700 USD

Applicants must be eligible for any required U.S. export authorizations.