Senior Formal Verification Engineer - LPU

For our client, a leader in the Telecommunications & Hardware space, we are seeking a Senior Formal Verification Engineer to join their team. This role leads work at the intersection of data, AI-enabled capabilities, and scalable technology delivery, collaborating across engineering, product, operations, and business stakeholders to translate complex requirements into practical solutions.

Responsibilities

• Verify AI-related sophisticated ASIC designs and features using formal verification methods
• Collaborate with architecture and RTL teams to specify properties and resolve design issues
• Leverage formal verification to verify design properties and ensure specification compliance
• Articulate formal verification coverage to partners
• Develop and implement advanced formal verification environments and methodologies for complex ASIC designs
• Train and mentor junior engineers on formal techniques and processes
• Support silicon bring-up and debug using formal methods

Qualifications

• BS/MS/PhD or equivalent experience in CS, CE, or EE
• 12+ years in ASIC verification with 8+ years focused on formal verification methods
• Mastery of SystemVerilog Assertions (SVA) and formal property verification
• Proficient in at least one popular formal verification tool (e.g., JasperGold, VC Formal)
• Good scripting skills for flow automation (Tcl, Python, etc.)
• Strong written and oral communication skills
• Keen attention to detail

Benefits

• Comprehensive benefits package including health, wellness, and retirement plans
• Opportunities for personal and professional growth in a supportive environment
• Access to cutting-edge technology and projects at the forefront of AI innovation
• Potential for equity and performance-based bonuses

Pay

$195,000 – $245,000 annually

Location: Remote (US-based candidates only; no visa sponsorship available)