Senior Engineer - HBM Design for Test (DFT)

About the role

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Senior Engineer – HBM Design for Test (DFT) is an experienced technical contributor responsible for the definition, implementation, integration, and support of DFT solutions across HBM core die and base die for current and next‑generation HBM products. This role focuses on driving defined DFT architectures, contributing to DFT specifications, and partnering with multi‑functional teams to ensure DFT features meet test, quality, and manufacturability requirements. The Senior Engineer works closely with DFT Architecture, Design Engineering, Product Engineering, Test, and DFT Verification to support successful tape‑out, silicon bring‑up, and qualification.

Responsibilities

• Implement and integrate DFT features for assigned HBM core die and base die designs in alignment with established DFT architecture and guidelines
• Contribute to the development, review, and maintenance of DFT specifications, requirements, and implementation guidelines
• Ensure DFT implementations support high‑quality, efficient, and manufacturable HBM products
• Collaborate with Design Engineering, Product Engineering, Test, and DFT Verification to:
  • Translate manufacturing and test requirements into actionable DFT implementations
  • Support alignment between DFT specifications and verification coverage
  • Identify, debug, and resolve DFT‑related issues during build execution, tape‑out, and silicon bring‑up
• Serve as a DFT contributor or sub‑domain owner for assigned programs or functional areas
• Support reuse and standardization of DFT logic and methodologies across HBM products under mentorship from DFT architecture leadership
• Participate in design, verification, and readiness reviews, providing technical guidance and issue resolution support
• Document DFT implementations, lessons learned, and procedures to support organizational knowledge exchange

Qualifications

• Bachelor’s degree in Electrical Engineering or related field (Master’s preferred)
• 5+ years of experience in semiconductor development with exposure to DFT, design, verification, test, or silicon debug
• 1+ years of experience in memory architectures (HBM or DRAM preferred)
• 1+ years of experience implementing DFT features and supporting DFT‑related debug and bring‑up activities

Preferred Qualifications

• Experience working with DFT verification teams and coverage methodologies
• Familiarity with manufacturing test flows and test requirements for advanced memory products
• Strong written and verbal communication skills
• Analog/Digital design and verification experience in Cadence environments