Senior Engineer, GPU RTL Power

Position Summary

Samsung, a world leader in advanced semiconductor technology, is seeking a Senior GPU RTL Power Engineer to join the GPU Project and RTL team at SARC/ACL. This role involves contributing to power optimization efforts for GPU blocks and subsystems, delivering industry-leading energy efficiency for Samsung’s next-generation mobile GPUs.

Role And Responsibilities

• Contribute to power optimization efforts for GPU blocks and subsystems, delivering industry-leading energy efficiency for Samsung’s next-generation mobile GPUs used in premium smartphones and adjacent market segments.
• Partner closely with hardware, software, and system-level design teams to support architectural, microarchitectural, and RTL-level power optimization strategies.
• Bring curiosity and knowledge in GPU/CPU microarchitecture, RTL power analysis, and low-power design techniques, and collaborate with teams to implement power-saving techniques, such as clock gating, voltage scaling, and low-power modes.
• Support technical excellence by collaborating with RTL designers, performance architects, modeling, implementation, and validation teams to implement power-saving techniques, such as clock gating, voltage scaling, and low-power modes, to deliver IP designs with market-differentiating power and performance results.
• Help advance cross-functional collaboration with hardware, software, and system teams to align power optimization strategies with architectural intent, workload behaviors, and system-level performance goals, while maintaining clear documentation of methodologies, strategy, results, and best practices.
• Take initiatives on moderate-to-complex projects and help advance best practices, methodologies by staying ahead of emerging GPU technologies and exploring new power-optimizing techniques.

Skills And Qualifications

• 2+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or a Master's degree.
• Hands-on experience in GPU/CPU architecture, microarchitecture, and high-performance digital design with PPA tradeoffs.
• Familiarity with RTL power analysis and optimization using tools such as PowerArtist, PTPX, Empower, or equivalent.
• Working knowledge of SystemVerilog and ASIC design flow, including RTL design, synthesis, timing analysis, and power optimization.
• Familiarity with low-power design techniques, including clock gating, power gating, and managing dynamic vs. leakage power tradeoffs.
• Proficiency with scripting languages such as Python or Perl.
• Understanding of physical design and STA flows and their interaction with power optimization.
• Excellent debugging, analytical, and problem-solving skills using data-driven approach.
• Excellent written and verbal communication skills for documenting designs, methodologies, and best practices.
• Excellent collaboration skills, with the ability to navigate ambiguity in a fast-paced, global team environment.