Senior Emulation Engineer

About the role

Ventana is building the highest-performance RISC-V CPUs on the planet—designed for data center, AI, and edge workloads, with real silicon, not slideware. Our second-generation Veyron core (V2) is on track to ship early next year, featuring an aggressive wide-issue pipeline and built in 4nm. Development on Veyron V3 is ramping now, with even greater performance and deep AI platform integration. This is your opportunity to work alongside engineers who built iconic processors like the AMD K6 and the first 64-bit ARM server processor (X-Gene at AppliedMicro)—bringing decades of CPU innovation to a clean-slate, open-standards future.

Responsibilities

• Work cross-functionally between all pre-silicon disciplines (arch/uarch, design, DV, software, performance, emulation/prototyping)
• Develop, debug, and maintain complex system level hybrid execution environments
• Enable pre-silicon bring up of system software and performance benchmarking workloads

Requirements

• 8+ years industry experience
• Bachelor’s or Master’s or PhD degree in related engineering field
• Ability to take initiative, work independently and across geographies
• Strong domain knowledge of computer architecture

Qualifications Desired

• Hands on experience with commercial emulation (Cadence Palladium, Mentor Veloce) and/or prototyping (Cadence Protium, HAPS) solutions: transactor development, virtual prototyping, implementation/enablement of flows for advanced verification techniques (assertions, coverage, UPF)
• Good understanding of modern SystemVerilog for design and verification
• Strong software development experience in compiled (C/C++) and interpreted (Python, Tcl) languages
• Strong hardware/software co-debug skills
• Exposure to isolating and reproducing silicon bugs in emulation
• Crisp and clear communication skills