Senior Electrical Engineer - FPGA Verification

U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance. The ability to obtain and maintain a U.S. government-issued DoD Secret security clearance is required; an active and existing clearance is required after day one.

About the Role

Raytheon brings over 100 years of engineering expertise to deliver solutions that defend freedoms and deter aggression, creating a safer, more secure world. The Radar Digital Products (RDP) Department is seeking an experienced Senior Electrical Engineer to verify FPGA-based designs for control and/or signal processing radar applications. This position is available at either the Tewksbury, MA or Marlborough, MA location and is onsite.

Responsibilities

• Own or contribute to the successful completion of FPGA-based designs, on time and on budget
• Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage using UVM
• Create complete documentation including verification plan and report
• Demonstrate self-motivation, with little supervision required
• Work cooperatively with systems, hardware, software engineers, and program management to ensure product success
• Support internal and external technical reviews

Requirements

• Typically requires a degree in Science, Technology, Engineering, or Mathematics (STEM) and a minimum of 5 years of prior relevant experience
• Digital design verification experience
• Proficient in SystemVerilog for verification
• Hands-on experience verifying designs using UVM-based testbenches
• Experience with industry-standard simulators (e.g., Questa, VCS, Xcelium)

Preferred Qualifications

• Experience designing FPGAs using VHDL/Verilog
• Solid understanding of constrained-random verification and functional coverage methodology
• Familiarity with AXI, PCIe, Ethernet, DDR protocols
• Experience with regression management and debug of complex, intermittent failures
• Ability to develop and maintain verification plans tied to design specifications and coverage closure criteria
• Experience with version control systems (e.g., Git, ClearCase, SVN) in a team-based development environment
• Proficiency with Git: branching strategies, pull requests, and collaborative workflows
• Experience with UVMF (UVM Framework) for structured, reusable testbench development
• Familiarity with Vivado and Quartus FPGA simulation flows
• Experience with scripting languages (Python, Tcl, Perl) for test automation and tooling
• Familiarity with SLURM workload manager for job scheduling and compute cluster resource management
• Prior experience mentoring junior verification engineers
• Existing DoD security clearance

Benefits

• Medical, dental, and vision insurance
• Life insurance, short-term disability, and long-term disability
• 401(k) match
• Flexible spending accounts
• Flexible work schedules
• Employee assistance program
• Employee Scholar Program
• Parental leave
• Paid time off and holidays
• Annual short-term and/or long-term incentive compensation programs (eligibility dependent on role level and collective-bargaining agreement status)

This position is eligible for relocation.

Pay

The salary range for this role is 86,800 USD - 165,200 USD. The range provided is a good faith estimate representative of all experience levels. RTX considers several factors when extending an offer, including but not limited to, the role, function and associated responsibilities, a candidate’s work experience, location, education/training, and key skills.