Senior Electrical Engineer-FPGA Verification

Date Posted: 2026-04-16 | Location: Marlborough, MA (alternate location: Tewksbury, MA) | Onsite role

U.S. citizenship is required; ability to obtain and maintain an active DoD Secret security clearance is mandatory from day one.

About the Role

RTX, the world’s largest aerospace and defense company, is seeking an experienced Senior Electrical Engineer to verify FPGA-based designs for control and/or signal processing radar applications within the Radar Digital Products (RDP) Department.

Responsibilities

• Own or contribute to the successful completion of FPGA-based designs, ensuring on-time and on-budget delivery.
• Verify designs using self-checking techniques with directed and constrained random tests, tracking functional and code coverage with UVM.
• Create complete documentation, including verification plans and reports.
• Demonstrate self-motivation with minimal supervision.
• Collaborate with systems, hardware, software engineers, and program management to ensure product success.
• Support internal and external technical reviews.

Requirements

• Degree in Science, Technology, Engineering, or Mathematics (STEM) with a minimum of 5 years of relevant experience.
• Proven experience in digital design verification.
• Proficiency in SystemVerilog for verification.
• Hands-on experience verifying designs using UVM-based testbenches.
• Experience with industry-standard simulators (e.g., Questa, VCS, Xcelium).

Preferred Qualifications

• Experience designing FPGAs using VHDL/Verilog.
• Solid understanding of constrained-random verification and functional coverage methodology.
• Familiarity with AXI, PCIe, Ethernet, and DDR protocols.
• Experience with regression management and debugging complex, intermittent failures.
• Ability to develop and maintain verification plans tied to design specifications and coverage closure criteria.
• Experience with version control systems (e.g., Git, ClearCase, SVN) in a team-based environment.
• Proficiency with Git, including branching strategies, pull requests, and collaborative workflows.
• Experience with UVMF (UVM Framework) for structured, reusable testbench development.
• Familiarity with Vivado and Quartus FPGA simulation flows.
• Experience with scripting languages (Python, Tcl, Perl) for test automation and tooling.
• Familiarity with SLURM workload manager for job scheduling and compute cluster resource management.
• Prior experience mentoring junior verification engineers.
• Existing DoD security clearance.

Benefits

• Medical, dental, and vision insurance.
• Life insurance, short-term disability, and long-term disability coverage.
• 401(k) match.
• Flexible spending accounts.
• Flexible work schedules.
• Employee assistance program.
• Employee Scholar Program (education support).
• Parental leave.
• Paid time off and holidays.
• Eligibility for annual short-term and/or long-term incentive compensation programs (dependent on role level and collective-bargaining agreements).

Relocation assistance is available for this position.

Pay

The salary range for this role is $86,800 – $165,200 USD. The final offer considers factors such as role, function, responsibilities, work experience, location, education/training, and key skills.