Senior Director, Architecture Research Lab

About the role

The Senior Director, Architecture Research Lab leads cutting-edge research on next-generation AI system architectures, focusing on end-to-end co-design of AI workloads, system-level modeling, hardware platforms, and high-performance processors that leverage Samsung's advanced memory technologies.

Responsibilities

• Define system-level architectures that solve memory-capacity, bandwidth, and interconnect challenges for large AI workloads (e.g., large language models, recommendation systems).
• Build and maintain analytical and event-driven simulation frameworks for compute-memory-network performance at rack scale.
• Conduct design-space exploration and quantitative trade-off studies (performance, power, cost) to guide architecture decisions.
• Partner with SAIT HQ teams to align modeling insights with real-world AI system implementations.
• Architect high-performance, out-of-order RISC-V CPU cores that serve as host processors for AI computing systems.
• Drive IPC-focused feature path-finding; lead micro-architecture research through performance-model simulation and workload analysis.
• Produce detailed micro-architecture specifications and guide cache/memory hierarchy design for optimal AI workload execution.
• Lead a multidisciplinary research team, set technical roadmaps, and ensure delivery of high-impact publications.
• Present architectural insights and strategic recommendations to senior leadership and external partners.

Requirements

• Education: Ph.D. in Computer Science, Electrical Engineering, or a related field.
• Experience: 10 + years in system-level architecture research or large-scale computing platform design, with a strong focus on AI workloads.
• Technical Expertise:
• Performance modeling, event-driven simulation, and quantitative analysis of compute-memory-interconnect systems.
• Deep knowledge of modern CPU/accelerator architectures (RISC-V, ARM, x86) and heterogeneous integration.
• Proven ability to design rack-scale AI system architectures that address memory, bandwidth, and interconnect constraints.
• Proficiency with transaction-level modeling (TLM) and event-driven simulation for compute-memory-network co-design.
• Experience in large-scale design-space exploration and PPA (performance, power, area/cost) trade-off analysis.
• Expertise in architecture and micro-architecture design of out-of-order CPUs.
• Hands-on experience with simulation tools and programming languages such as Python and C++.

Qualifications

• Excellent written and verbal communication; proven ability to deliver technical presentations to senior stakeholders.
• Preferred Experience:
• Proven track record of publishing high-impact research papers.
• Experience influencing product roadmaps through architectural recommendations.
• Strong collaborative history with cross-functional teams (hardware, software, memory technology).
• Inclusive, adapting your style to the situation and diverse global norms of our people.
• Avid learner, curious and resilient, seeking data to build understanding.
• Collaborative, building relationships, offering support, and welcoming approaches.
• Innovative and creative, exploring new ideas and adapting quickly to change.

Skills

• Advanced knowledge of AI system architectures and RISC-V CPU design.
• Experience with transaction-level modeling and event-driven simulation.
• Strong communication and presentation skills.
• Ability to manage a multidisciplinary research team.
• Experience with large-scale design-space exploration and PPA trade-off analysis.
• Knowledge of out-of-order CPU architectures and micro-architecture design.
• Proficiency with simulation tools and programming languages like Python and C++.

Benefits

Base Pay Range: $246,000 - $430,000 USD

Additional benefits include:

• Charitable giving match
• Frequent volunteer opportunities
• 4+ weeks of paid time off annually
• Support for fertility care, medical travel, and virtual pet care
• On-demand mental health resources
• On-site fitness center and wellness programs
• Flexible work arrangements

Pay

$246,000 - $430,000 USD

Schedule

Daily onsite presence at our San Jose Headquarters in alignment with our Flexible Work policy

Qualifications

• Education: Ph.D. in Computer Science, Electrical Engineering, or a related field.
• Experience: 10 + years in system-level architecture research or large-scale computing platform design, with a strong focus on AI workloads.
• Technical Expertise:
• Performance modeling, event-driven simulation, and quantitative analysis of compute-memory-interconnect systems.
• Deep knowledge of modern CPU/accelerator architectures (RISC-V, ARM, x86) and heterogeneous integration.
• Proven ability to design rack-scale AI system architectures that address memory, bandwidth, and interconnect constraints.
• Proficiency with transaction-level modeling (TLM) and event-driven simulation for compute-memory-network co-design.
• Experience in large-scale design-space exploration and PPA (performance, power, area/cost) trade-off analysis.
• Expertise in architecture and micro-architecture design of out-of-order CPUs.
• Hands-on experience with simulation tools and programming languages such as Python and C++.

Skills

• Advanced knowledge of AI system architectures and RISC-V CPU design.
• Experience with transaction-level modeling and event-driven simulation.
• Strong communication and presentation skills.
• Ability to manage a multidisciplinary research team.
• Experience with large-scale design-space exploration and PPA trade-off analysis.
• Knowledge of out-of-order CPU architectures and micro-architecture design.
• Proficiency with simulation tools and programming languages like Python and C++.

Benefits

Base Pay Range: $246,000 - $430,000 USD

Additional benefits include:

• Charitable giving match
• Frequent volunteer opportunities
• 4+ weeks of paid time off annually
• Support for fertility care, medical travel, and virtual pet care
• On-demand mental health resources
• On-site fitness center and wellness programs
• Flexible work arrangements

Pay

$246,000 - $430,000 USD

Schedule

Daily onsite presence at our San Jose Headquarters in alignment with our Flexible Work policy

Qualifications

• Education: Ph.D. in Computer Science, Electrical Engineering, or a related field.
• Experience: 10 + years in system-level architecture research or large-scale computing platform design, with a strong focus on AI workloads.
• Technical Expertise:
• Performance modeling, event-driven simulation, and quantitative analysis of compute-memory-interconnect systems.
• Deep knowledge of modern CPU/accelerator architectures (RISC-V, ARM, x86) and heterogeneous integration.
• Proven ability to design rack-scale AI system architectures that address memory, bandwidth, and interconnect constraints.
• Proficiency with transaction-level modeling (TLM) and event-driven simulation for compute-memory-network co-design.
• Experience in large-scale design-space exploration and PPA (performance, power, area/cost) trade-off analysis.
• Expertise in architecture and micro-architecture design of out-of-order CPUs.
• Hands-on experience with simulation tools and programming languages such as Python and C++.

Skills

• Advanced knowledge of AI system architectures and RISC-V CPU design.
• Experience with transaction-level modeling and event-driven simulation.
• Strong communication and presentation skills.
• Ability to manage a multidisciplinary research team.
• Experience with large-scale design-space exploration and PPA trade-off analysis.
• Knowledge of out-of-order CPU architectures and micro-architecture design.
• Proficiency with simulation tools and programming languages like Python and C++.

Benefits

Base Pay Range: $246,000 - $430,000 USD

Additional benefits include:

• Charitable giving match
• Frequent volunteer opportunities
• 4+ weeks of paid time off annually
• Support for fertility care, medical travel, and virtual pet care
• On-demand mental health resources
• On-site fitness center and wellness programs
• Flexible work arrangements

Pay

$246,000 - $430,000 USD

Schedule

Daily onsite presence at our San Jose Headquarters in alignment with our Flexible Work policy

Qualifications

• Education: Ph.D. in Computer Science, Electrical Engineering, or a related field.
• Experience: 10 + years in system-level architecture research or large-scale computing platform design, with a strong focus on AI workloads.
• Technical Expertise:
• Performance modeling, event-driven simulation, and quantitative analysis of compute-memory-interconnect systems.
• Deep knowledge of modern CPU/accelerator architectures (RISC-V, ARM, x86) and heterogeneous integration.
• Proven ability to design rack-scale AI system architectures that address memory, bandwidth, and interconnect constraints.
• Proficiency with transaction-level modeling (TLM) and event-driven simulation for compute-memory-network co-design.
• Experience in large-scale design-space exploration and PPA (performance, power, area/cost) trade-off analysis.
• Expertise in architecture and micro-architecture design of out-of-order CPUs.
• Hands-on experience with simulation tools and programming languages such as Python and C++.

Skills

• Advanced knowledge of AI system architectures and RISC-V CPU design.
• Experience with transaction-level modeling and event-driven simulation.
• Strong communication and presentation skills.
• Ability to manage a multidisciplinary research team.
• Experience with large-scale design-space exploration and PPA trade-off analysis.
• Knowledge of out-of-order CPU architectures and micro-architecture design.
• Proficiency with simulation tools and programming languages like Python and C++.

Benefits

Base Pay Range: $246,000 - $430,000 USD

Additional benefits include:

• Charitable giving match
• Frequent volunteer opportunities
• 4+ weeks of paid time off annually
• Support for fertility care, medical travel, and virtual pet care
• On-demand mental health resources
• On-site fitness center and wellness programs
• Flexible work arrangements