Senior Director, Architecture Research Lab

About the role

Advancing the World's Technology Together
Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.

Responsibilities

• Lead cutting-edge research on next-generation AI system architectures.
• Define system-level architectures that solve memory-capacity, bandwidth, and interconnect challenges for large AI workloads (e.g., large language models, recommendation systems).
• Build and maintain analytical and event-driven simulation frameworks for compute-memory-network performance at rack scale.
• Conduct design-space exploration and quantitative trade-off studies (performance, power, cost) to guide architecture decisions.
• Partner with SAIT HQ teams to align modeling insights with real-world AI system implementations.
• Architect high-performance, out-of-order RISC-V CPU cores that serve as host processors for AI computing systems.
• Drive IPC-focused feature path-finding; lead micro-architecture research through performance-model simulation and workload analysis.
• Produce detailed micro-architecture specifications and guide cache/memory hierarchy design for optimal AI workload execution.
• Lead a multidisciplinary research team, set technical roadmaps, and ensure delivery of high-impact publications.
• Present architectural insights and strategic recommendations to senior leadership and external partners.

Requirements

• Ph.D. in Computer Science, Electrical Engineering, or a related field.
• 10 + years in system-level architecture research or large-scale computing platform design, with a strong focus on AI workloads.
• Deep knowledge of modern CPU/accelerator architectures (RISC-V, ARM, x86) and heterogeneous integration.
• Experience in large-scale design-space exploration and PPA (performance, power, area/cost) trade-off analysis.
• Expertise in architecture and micro-architecture design of out-of-order CPUs.
• Hands-on experience with simulation tools and programming languages such as Python and C++.

Qualifications

• Excellent written and verbal communication; proven ability to deliver technical presentations to senior stakeholders.
• Proven track record of publishing high-impact research papers.
• Experience influencing product roadmaps through architectural recommendations.
• Strong collaborative history with cross-functional teams (hardware, software, memory technology).
• Inclusive, adapting your style to the situation and diverse global norms of our people.
• Avid learner, approaching challenges with curiosity and resilience, seeking data to help build understanding.
• Collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, proactively exploring new ideas and adapting quickly to change.

Skills

• Performance modeling, event-driven simulation, and quantitative analysis of compute-memory-interconnect systems.
• Transaction-level modeling (TLM) and event-driven simulation for compute-memory-network co-design.
• Out-of-order CPU architecture design.
• Simulation tools and programming languages such as Python and C++.

Benefits

• Base Pay Range: $246,000 - $430,000 USD
• Comprehensive benefits including Medical/Dental/Vision coverage, 401(k), and more.
• Charitable giving match and frequent volunteer opportunities.
• Flexible work arrangements and wellness programs.

Pay

The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience.

Schedule

Daily onsite presence at our San Jose Headquarters in alignment with our Flexible Work policy.