Senior Digital/AMS Validation and Integration Engineer

Key Responsibilities

• Develop and integrate RTL (Verilog/SystemVerilog) for control loops, calibration engines, and high-speed data paths in 10G+ transceivers.
• Define and implement the digital interface for analog blocks (ADCs, PLLs, Driver stages), ensuring robust signal crossing between asynchronous domains.
• Lead the digital implementation flow, working closely with the physical design team to achieve timing closure in high-speed clock domains.
• Partner with the validation team to bring up silicon. Use Python-based tools to exercise RTL features, debug state machines, and verify registers (CSRs) in real-time hardware.
• Execute block-level and chip-level simulations to ensure digital control logic correctly handles analog PVT variations and startup sequences.

Skills & Qualifications

• Education: BSEE/MSEE with 5–8+ years of experience in Digital RTL Design or Digital Integration.
• HDL Expertise: Advanced proficiency in SystemVerilog/Verilog for synthesis.
• Timing & Implementation: Strong understanding of Static Timing Analysis (STA), clock domain crossing (CDC), and constraints (SDC).
• Scripting & Automation: Deep experience with Python or Perl for hardware control, test automation, and data processing.
• Lab Skills: Proficient in using logic analyzers, high-speed scopes, and JTAG/I2C/SPI protocols for on-chip debugging.
• Preferred Experience: Experience with 10GBase-T, ASA, or Automotive Ethernet standards.
• Familiarity with the hand-off between digital logic and high-speed Analog Front Ends (AFE).
• Knowledge of DFT (Design for Test) and BIST (Built-In Self-Test) insertion for high-speed links.
• Able to create Verilog-A models.