Senior Design Verification Engineer – High Performance CPU Core

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications. Our unrivaled compute platforms enable leading technology companies to innovate across markets including artificial intelligence, machine learning, automotive, data center, mobile, and consumer.

About the role

SiFive is looking for a Senior Design Verification Engineer to drive functional verification of high-performance CPU core units. This role focuses on high-performance out-of-order core verification, with potential scope across areas such as Frontend, Midcore, Load-Store Unit, and Hardware Prefetch. You will work closely with architecture, RTL, performance, and verification teams to ensure design intent is verified correctly, risks are identified early, and signoff quality is achieved with strong technical execution.

Responsibilities

• Own verification planning and execution for assigned high-performance CPU core areas, from block-level verification through core-level integration.
• Create effective verification strategies and test plans based on CPU architecture and microarchitectural behavior.
• Develop and maintain robust verification environments, testbenches, checkers, scoreboards, assertions, stimulus, and coverage models.
• Define and execute directed and constrained-random tests that expose corner cases in branch prediction, instruction fetch, pipeline interactions, issue/dispatch behavior, hazard handling, load/store ordering, memory consistency, and hardware prefetch behavior.
• Analyze failures, isolate root cause, and drive fixes across RTL, testbench infrastructure, assertions, and test content.
• Collaborate closely with architecture and design teams to review specifications, identify ambiguities early, and improve verification quality and debugability.
• Write functional coverage, analyze code and functional coverage, and close coverage gaps to ensure verification completeness and signoff quality.
• Contribute to reusable DV methodology, automation, and infrastructure that improve team productivity and verification quality across future core generations.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 3+ years of relevant experience in IP, CPU/core, or SoC functional verification, preferably with experience in CPU/core verification.
• Strong hands-on experience with SystemVerilog and UVM-based verification methodologies.
• Solid understanding of computer architecture and CPU microarchitecture fundamentals.
• Experience with test planning, testbench development, constrained-random verification, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution.
• Strong programming and scripting fundamentals for building scalable verification solutions.

Preferred Qualifications

• Direct experience with high-performance out-of-order core verification.
• Experience in one or more of the following areas: Frontend, Midcore, Load-Store Unit, memory ordering and consistency, or hardware prefetch verification.
• Familiarity with formal verification, emulation, or performance-oriented verification flows.
• Experience collaborating across architecture, performance, compiler, system verification, and software teams.
• Experience building reusable infrastructure and improving team-wide verification methodology.

What Success Looks Like

• Verification plans capture the real architectural and microarchitectural risks early and completely.
• Difficult CPU bugs are found early, debugged efficiently, and closed with durable solutions.
• Coverage quality and verification productivity improve meaningfully under your ownership.
• Architecture, design, and DV teams view you as a strong technical contributor for challenging high-performance CPU verification problems.

Benefits

This role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more.

Pay

In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity.