Senior Design Verification Engineer (eInfochips Inc)

What You'll Be Doing

• Testbenches: Build scalable verification environments using UVM and SystemVerilog.
• Planning: Create detailed verification plans from architectural specifications.
• Execution: Write, run, and debug constrained-random tests and directed tests.
• Coverage: Define, measure, and close functional and code coverage metrics.
• Gate-Level: Run gate-level simulations to verify power-up and timing states.
• Automation: Develop scripts to automate regression runs and triage failures.

What We Are Looking For

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Languages: Strong proficiency in SystemVerilog and scripting (Python, Perl, or Tcl).
• Methodology: Hands-on experience with UVM (Universal Verification Methodology).
• Tools: Experience with industry-standard simulators Cadence Xcelium preferred, but experience with Synopsys VCS, or Siemens Questa will translate.
• Concepts: Deep understanding of constrained-random verification, assertions (SVA), and functional coverage.
• Protocols: Knowledge of common protocols like AMBA (AXI/AHB/APB).

Preferred Qualifications

• Experience with formal verification tools and methodologies.
• Background in power-aware verification using UPF/CPF.
• Experience verifying custom ARM or DSP processor cores.
• Familiarity with emulation platforms like Palladium.
• Experience with: MMU verification, SRAM/ memory subsystem verification.
• Nice-to-have: DSP verification experience, Modeling (RNM / behavioral models).

Scope of Work

• Verification at system/subsystem level, using SV/UVM + C-based testing, with emulation (Cadence Palladium).
• New co-processing subsystem ((with NPU, MMU, SRAM, AXI).
• Memory subsystem interactions.
• DSP/signal processing.
• SystemVerilog + UVM-based verification.
• C-based test development (processor-in-loop simulation).
• Use of emulation platforms (Cadence Palladium or similar).
• Some modeling using Real Number Models (RNM) for analog/digital interaction.

Key Skills Needed

• Strong DV fundamentals.
• Experience with: MMU verification, SRAM/memory subsystem verification, Bus protocols (AXI transition mentioned).
• Nice-to-have: DSP verification experience, Modeling (RNM / behavioral models).

What’s In It For You

• Competitive financial compensation.
• Solid benefits package.
• Medical, Dental, Vision Insurance.
• 401k, With Matching Contributions.
• Short-Term/Long-Term Disability Insurance.
• Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options.
• Paid Time Off (including sick, holiday, vacation, etc.).
• Tuition Reimbursement.
• Growth Opportunities.
• More!

About eInfochips

• eInfochips, an Arrow company (Fortune #154), is a leading global provider of product engineering and semiconductor design services.
• A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals.
• eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few.
• Along with Arrow’s $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients.
• eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients.

EEO Statement

• Equal opportunity employer.
• All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status.