Senior Debug Verification Engineer

About the role

This role involves designing and verifying debug architecture for complex SoC, FPGA, and full chip designs. Responsibilities include creating test cases and test benches using UVM methodology, full chip/system functional verification, and coordinating cross-functional efforts with the Design, SW, and Architecture teams.

Responsibilities

• Create test cases and test benches using UVM methodology
• Perform full chip/system functional verification, defining verification strategies, methodologies, and test plans
• Coordinate cross-functional efforts with Design, SW, and Architecture teams to achieve full coverage verification
• Verify performance using system applications and identify shortfalls
• Engage in pre-silicon system verification, including SoC, FPGA, and full chip design verification
• Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification
• Experience with ARM and RISC Debug Architectures is desired, with a focus on design verification
• Prior working experience on UltraSoC/Tessent Embedded Analytics Debug Architecture is preferred but not mandatory
• Experience with emulation is an added advantage

Qualifications

• 8+ years of experience with complex ASIC designs and/or verification
• 8+ years of experience with SystemVerilog language
• 8+ years of experience on UVM verification methodology and formal verification methods
• 8+ years of experience scripting in Linux/Unix environments, including proficiency in Perl and/or Python
• Strong communication skills and ability to work effectively with a team spread across different geographical sites