Senior Verification Engineer

Responsibilities

• Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers.
• Build verification environments using SystemVerilog and UVM.
• Identify and write all types of coverage measures for corner-cases.
• Debug the functionality with design engineers.
• Perform coverage collection and follow the metrics to close the full functionality.

Requirements

• 10+ years of experience; At least 7 years of experience in verification - a must.
• In depth knowledge in VLSI verification flow, languages and concepts - a must.
• Performed at least 2 or more full block/system verification cycles.
• Deep experience in building verification environments using SystemVerilog and UVM or Specman or SystemC.
• Performed at least 2 or more full block/system verification cycles.
• Experience in data path or data protocols, specifically Ethernet - preferred.
• Verification using one of the known methodologies (eRM, UVM, OVM).

Nice to Haves

• Track record in identifying and writing all types of coverage measures for corner-cases.
• Planned and performed the verification of digital design blocks according to the design specification and interacting with design engineers.
• Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.
• Communication: Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.