Senior Cache Coherency Architect

About the role

This opportunity allows you to be part of a world-class organization that develops scalable, low-latency, high-bandwidth coherent interconnect systems. These systems power groundbreaking NVIDIA products such as Grace-CPU-Superchip, Grace-Hopper-Superchip, and Vera-Rubin.

Responsibilities

• Define consistent interconnect architecture, cache-coherency protocols, and high-performance on-chip interconnect interfaces.
• Contribute to interconnect IP block specifications, build, verification, and integration into the NoC fabric to ensure cache-coherency compliance.
• Collaborate with architects to guarantee the interconnect architecture aligns with project power, performance, and area (PPA) requirements.
• Develop and maintain functional and performance models for the NoC fabric and IP units to assist with analysis and validation.
• Collaborate with cross-functional design and verification teams (simulation, emulation, and formal) to ensure implementations align with architectural specifications.
• Support silicon bring-up and post-silicon debug as needed.

Requirements

• Master’s degree in electrical engineering, Computer Engineering, Computer Science, or equivalent experience.
• 5+ years of experience in processor design or other high-performance semiconductor designs.
• Deep understanding of cache coherency, with hands-on experience in industry-standard protocols (e.g., AXI, ACE, CHI).
• Experience authoring specifications and designing cache-coherent interconnects.
• Strong understanding of system and memory subsystem architecture, with a focus on cache-coherent interconnect.
• Experience developing coherent IP models (e.g., VIPs, BFMs) for simulation and emulation.
• Proficiency in C, C++, Python, and Verilog.

Qualifications

• Master’s degree in electrical engineering, Computer Engineering, Computer Science, or equivalent experience.
• 5+ years of experience in processor design or other high-performance semiconductor designs.

Skills

• Understanding of cache coherency, with hands-on experience in industry-standard protocols (e.g., AXI, ACE, CHI).
• Experience authoring specifications and designing cache-coherent interconnects.
• Strong understanding of system and memory subsystem architecture, with a focus on cache-coherent interconnect.
• Experience developing coherent IP models (e.g., VIPs, BFMs) for simulation and emulation.
• Proficiency in C, C++, Python, and Verilog.

Benefits

Join us and help build the future of computing at NVIDIA!

Pay

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 152,000 USD - 241,500 USD for Level 3, and 184,000 USD - 287,500 USD for Level 4.

Schedule

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.