CPU Cache Subsystem Senior Design Manager

About the role

In this role, you will contribute to all phases of complex designs of CPU subsystems from design specification to productization, including integration into target SOCs.

Responsibilities

• Lead and manage a team of design engineers working on CPU functional units, emphasizing on micro-architecture and RTL design for the next generation CPU subsystem.
• Review/propose performance enhancing micro-architecture features, and work with Software, Architecture, and Performance teams for trade-off studies. Communicate the pros and cons of micro-architecture enhancements.
• Deliver with plans on achieving project milestones and goals, towards a design that meets production quality on schedule.
• Work with the Verification team to ensure production of quality designs, and the Physical Design and Power teams to meet frequency, power, and area goals.
• Focus on load-store-unit and cache subsystem design and optimizations with other parts of CPU to deliver best Performance, Power, Area (PPA).

Qualifications

• Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 15 years of experience in CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including micro-architecture definition and PPA processing. Experience leading and managing teams for modern processor subsystems with high speed, lower power design. Experience with front-end quality checks (e.g., Lint, CDC/RDC).
• Preferred qualifications: Experience with ARM instruction set architecture, experience with mobile CPU subsystem, experience with mobile SOC architecture/integration.

Benefits

US: $240000 - $334000 (USD) + 25% bonus target + equity + benefits

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