Senior Avionics FPGA Design & Verification Engineer - TeraWave

About the role

Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide.

Responsibilities

• Design and develop digital hardware architectures for high reliability satellite avionics
• Create and implement RTL code for critical SoC blocks and interfaces
• Contribute to architecture optimization for performance, power, and cost trade-offs
• Collaborate on design verification to ensure robust and reliable designs
• Support prototype development for early validation
• Document design specifications, architecture decisions, and implementation details
• Participate in design reviews and technical discussions with cross-functional teams
• Debug complex digital design issues
• Implement interfaces between digital hardware and firmware/software components
• Research and evaluate new architectural approaches to meet evolving requirements

Requirements

• B.S. or higher in Electrical Engineering, Computer Engineering, or a related discipline
• 7+ years of experience in digital design and SoC architecture
• Proficiency in SystemVerilog or Verilog for RTL implementation
• Experience with SoC integration and interface design
• Understanding of digital timing and synchronization concepts
• Familiarity with industry-standard bus protocols (AXI, AHB, etc.)
• Experience with synthesis tools and RTL-to-gates methodology
• Experience with simulation and debugging of complex digital systems
• Solid knowledge of Field Programmable Gate Arrays (FPGA) and FPGA tool flow
• Strong background in simulation-based test using Questasim, and evaluation of code coverage metrics

Qualifications

• Minimum Qualifications
• Compensation Range For CA applicants is $156,802.00 - $219,522.45 CO applicants is $144,179.00 - $201,849.90 WA applicants is $156,802.00 - $219,522.45 Other Site Ranges May Differ

Skills

• SystemVerilog or Verilog for RTL implementation
• SoC integration and interface design
• Digital timing and synchronization concepts
• Industry-standard bus protocols (AXI, AHB, etc.)
• Synthesis tools and RTL-to-gates methodology
• Simulation and debugging of complex digital systems
• Field Programmable Gate Arrays (FPGA)
• Questasim and code coverage metrics

Benefits

• Medical, dental, vision, basic and supplemental life insurance
• Paid parental leave
• Short and long-term disability
• 401(k) with a company match of up to 5%
• Education Support Program
• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays

Pay

• For CA applicants is $156,802.00 - $219,522.45 CO applicants is $144,179.00 - $201,849.90 WA applicants is $156,802.00 - $219,522.45 Other Site Ranges May Differ

Schedule

• Not specified