Jobs · Engineering · Texas

Senior ASIC Physical Design Engineer, Netlisting

NVIDIA · Austin, TX · 1 wk ago
HybridEngineeringFull-time

About the role

NVIDIA is seeking a Senior ASIC Physical Design Engineer, Netlisting to join their dynamic team. The ideal candidate will have expertise in logic equivalence checking/FV, hardware architecture, and experience in clock-domain-crossing checking, MTBF analysis, and logic synthesis.

Responsibilities

  • Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, focusing on netlist-related aspects such as equivalence checking, asynchronous checking, logic synthesis, and netlist quality checks.
  • Help in all aspects of physical design, including driving timing convergence, timing constraints generation and management, and ECO generation and implementation.

Requirements

  • BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience.
  • Expertise in logic equivalence checking/FV required from RTL to tapeout with industry-standard tools.
  • Deep understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
  • Experience in clock-domain-crossing checking, MTBF analysis, either with industry-standard tools or in-house tools.
  • Background with logic synthesis at either block or full-chip level, at project execution and/or flow development.
  • Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
  • Expertise and in-depth knowledge of industry standard EDA tools in related fields.
  • Proficiency in programming and scripting languages, such as Perl, TCL, Make, Python, etc.

Qualifications

  • Experience in logic synthesis and equivalence checking/FV.
  • Familiarity with industry tools and flow.
  • Strong hands-on debugging capability and problem-solving skills.
  • Background in DFT timing closure for various modes e.g. scan shift and capture, transition faults, BIST, etc.

Skills

  • Experience with AI utilization to improve workflows and productivity.

Benefits

  • Competitive base salary ranging from $136,000 to $218,500 for Level 3 and $168,000 to $264,500 for Level 4.
  • Equity and benefits package.

Pay

Base salary range: $136,000 - $218,500 for Level 3, and $168,000 - $264,500 for Level 4.

Schedule

Not specified.

Benefits

Not specified.

Contact

Applications for this job will be accepted at least until July 3, 2026.

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