Senior ASIC DV Engineer
Broadcom · San Jose, CA · 2 mo ago
EngineeringFull-time
Responsibilities
- Architecting block and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces.
- Using thorough knowledge of mixed-signal simulations (AMS, Spice, etc), developing test plans and coverage metrics from specifications and writing block and chip-level tests.
- Debugging RTL and Gate simulations and working with design engineers to verify fixes.
- Writing diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.
- Replicating silicon bugs in simulation environments and validating fixes or SW workarounds.
- Converting verification tests to test patterns and assisting Test Engineers on ATE vector bring up.
- Evaluating latest verification methodologies and developing scripts etc. to automate verification flows.
Qualifications
- Bachelors in Engineering and 8+ years of related experience; at this level postgraduate coursework may be desirable or Masters degree in Engineering and 6+ years of related experience
- MS or PhD is preferred
Pay
The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
Benefits
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company paid holidays
- Paid sick leave and vacation time