Senior Asic Design Engineer

Job Title: Senior Asic Design Engineer Location: Dallas, TX (Onsite) Duration: 9 Months+ Interview Mode: Phone then Video Responsibilities: Designing and implementing Verilog / System Verilog blocks for image processing SoC. Location: On-site in Dallas, TX. (No remote option available at this time, although if the candidate is a superstar they would be considered.) Requirements: Experience with SoC/CPU/GPU architecture, AXI interconnects, high-speed interfaces, and high bandwidth techniques. Prefer 10+ years of industry hands-on RTL design experience, although 5+ years will be considered for the right candidate. Strong proficiency in Verilog / System Verilog. Skilled with design verification and functional coverage methodologies, including UVM (universal verification methodology) Job Responsibilities Experience with SoC/CPU/GPU architecture, AXI interconnects, high-speed interfaces, and high bandwidth techniques. Prefer 10+ years of industry hands-on RTL design experience, although would consider 5+ years for the right candidate. Strong proficiency in Verilog / System Verilog. Skilled with design verification and functional coverage methodologies, including UVM (universal verification methodology) Skills: soc,verilog,design,architecture,asic design,rtl design