Senior ASIC Design Verification Engineer, Silicon

About the role

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Responsibilities

• Architect, develop, and maintain advanced, end-to-end UVM testbenches from scratch for complex, scalable, and programmable IPs.
• Drive verification excellence by implementing sophisticated constrained random testing methodologies to uncover edge cases and achieve high confidence in IP robustness.
• Create and execute scalable testplans and coverage models designed to track, manage, and close requirements across multiple versions and iterations of the design.
• Lead debugging efforts at the IP and subsystem levels, identifying root causes of failures and working with designers to implement fixes.
• Act as a key liaison, interacting with multiple subsystem design and verification leads to understand unique requirements, engage in architectural discussions, and provide customizable verification solutions that bridge different subsystems.
• Mentor and guide junior verification engineers on design verification (DV) engineering best practices to elevate the team.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience verifying digital logic at the RTL level using SystemVerilog or C/C++.
• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
• Experience creating and using verification components and environments in standard verification methodologies (e.g., UVM, SVA, CRV, PSS, or LPDV).

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 10 years of experience with building verification methodologies that span simulation, formal, emulation, and FPGA prototyping.
• Experience with interconnect protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL).
• Experience with performance verification of SOCs, pre-silicon analysis and post-silicon correlation.
• Experience with scripting languages and software development frameworks.

Skills

• Advanced knowledge of SystemVerilog or C/C++ for RTL verification.
• Experience with UVM, SVA, CRV, PSS, or LPDV verification methodologies.
• Strong debugging and problem-solving skills.
• Excellent communication and collaboration skills.
• Ability to work independently and as part of a team.

Benefits

Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits