Senior ASIC Design Verification Engineer - LPU

About the role

NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the design and implementation of the world's leading inference accelerator. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities

• Verify the design and implementation of the ASIC design, architecture, reference models and micro-architecture using advanced verification methodologies
• Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design
• Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks
• Implement and optimize automated verification flows to improve productivity and efficiency
• Stay updated on the latest trends and advancements in ASIC design verification and incorporate innovative techniques into the verification process

Requirements

• Bachelors Degree in EE, CS or CE (or equivalent experience) and 8+ years of relevant industry experience
• Background with building block and SoC level testbench utilizing strong debugging and analytical skills
• Experience in verification using random stimulus along with functional coverage, assertion-based verification methodologies and tools
• Expertise in SystemVerilog and Universal Verification Methodology (UVM)
• Experience with design and verification tools (VCS, Verdi or equivalent)
• Background in UPF power verification is a plus
• Experience in netlist and DFT verification is a plus
• Perl/Python and C/C++ programming language experience desirable
• Knowledge of ASIC design flow, from specification to GDS
• Knowledge of applying machine learning to ASIC verification flow

Qualifications

• Competitive salaries and a generous benefits package
• Opportunity to work with the latest in GPU and AI technology
• Unprecedented growth and rapid team expansion

Benefits

• Equity and benefits eligibility

Pay

Base salary range: $168,000 - $264,500 for Level 4, and $196,000 - $310,500 for Level 5

Schedule

Not specified

Skills

• SystemVerilog
• Universal Verification Methodology (UVM)
• VCS, Verdi or equivalent tools
• UPF power verification
• Netlist and DFT verification
• Perl/Python and C/C++ programming languages
• ASIC design flow
• Machine learning for ASIC verification

Benefits

• Not specified

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