Senior ASIC Design Engineer - Terawave

Applications will be accepted on an ongoing basis until the requisition is closed.

About the role

Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. We are seeking ASIC/SOC Design engineers (all levels including Senior, Principal, Senior Principal) who are critical to ensuring our RFIC/ASIC designs culminate in thoroughly designed and validated cutting-edge integrated circuits that drive Blue Origin's mission of enabling millions to live and work in space for the benefit of Earth.

Location: This role is based on site in San Diego, CA; the Bay Area, CA; Austin, TX; Kent, WA.

Responsibilities

• Design and Verification
• Verilog/SystemVerilog experience in designing complex SOCs
• CDC, RDC, LINT
• Write requirements, specification and test plans
• Optimize performance while keeping power low
• Clock gating (dynamic and static)
• Multi-voltage SOC front end design
• Formal verification
• Functional coverage, definition and collection
• Module verification
• Complex subsystem verification
• Complex SoC verification
• Cosimulation with software, integration of software build tool flow with simulation
• Gate simulation
• External IP integration
• ARM CPU single and multi-core integration with bus fabric, GIC, cache, MMU, secure boot
• AXI bus complex
• High performance DMA
• NOC integration
• DDR, PCIE, Ethernet, SPI integration
• High speed serdes integration
• DSP structures (FIR, Cordic, FFT/IFFT, MAC, circular buffers, analog-digital interface)
• Modem using state of the art DSP, coding, framing (phy and MAC)
• Sequenced and time bound data movement in DSP structures (time slots, time stamps etc)
• SOC top level integration using models for analog macros
• Verification using golden reference models in Matlab, SystemC or C
• Code coverage
• Timing constraints
• Support back-end teams during DFT, LEC, floorplan, STA
• Post-Silicon
• Post silicon bring up
• FPGA ASIC to/from FPGA flow

Requirements

• BS, MS in Electrical Engineering or a related technical field
• 8+ years of experience
• Deep working knowledge and hands on experience in innovative verification flows
• Applicants for employment at Blue Origin must be a U.S. citizen or national, U.S. permanent resident (i.e. current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum

Benefits

• Medical, dental, vision, basic and supplemental life insurance
• Paid parental leave
• Short and long-term disability
• 401(k) with a company match of up to 5%
• Education Support Program
• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays
• Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion

Pay

Base Pay Range:

• For CA applicants: $230,398.00 - $322,556.85
• For WA applicants: $230,398.00 - $322,556.85
• Other site ranges may differ