Senior Applications and Solutions Engineer - Foundry Services

Key Responsibilities

• Provide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows and digital design signoff methodologies in multi-voltage domain implementation and verification.
• Support and deliver ASIC/Digital tool/flow/methodology solutions, especially in multi-voltage domain design implementation and verification using Cadence and Synopsys tool suites.
• Have deep knowledge of UPF/CPF (level-shifter, isolation, power gating, retention, always-on) implementation and verification using (VCLP and Conformal LP).
• Have experience in writing and debugging UPF/CPF for multi-voltage domain designs.
• Drive customer success through expert guidance and have strong hand-on experience in ASIC design execution.

Core Competencies

• Self-driven and results-oriented with ability to manage multiple tasks effectively.
• Strong teamwork skills to drive solutions for implementation challenges.
• Analytical problem-solving capabilities for complex design issues.
• Excellent communication skills with experience in collaboration and customer feedback.

Qualifications

• US Citizenship required.
• Ability to obtain a US Government Security Clearance.
• Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• 4+ years of experience with advanced CMOS processes (16nm and below).
• 3+ years of experience in ASIC design implementing and verification in area of low power, multi-voltage domain.
• 3+ years of experience in scripting languages like Python, Perl, Tcl, and/or shell scripting.

Preferred Qualifications

• Active US Government Security Clearance with a minimum of Secret level.
• Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• Experience with state-of-the-art process technology (7nm and below).
• Hands-on experience in physical design Implementation and verification methodology for multi-voltage domain in SoC design.
• Experience using EDA tools for multi-power domain design (UPF/CPF) implementation and power-intent verification (VCLP, Conformal LP) at block and at SOC level.
• Experience in writing and debugging UPF/CPF for multi-voltage domain designs.
• Customer-facing experience in technical support roles.

Pay

$122,440.00 - 232,190.00 USD

Schedule

Shift 1 (United States of America)