Senior Analog Validation/Characterization Engineer

Key Responsibilities

• Create and maintain behavioral models (SystemVerilog/RNM, Verilog-A) for mixed-signal blocks to support full-chip functional verification.
• Perform bench-top characterization of high-speed transceivers (10G+) using standard lab equipment (Oscilloscopes, VNAs, BERTs).
• Develop and optimize Python scripts to automate lab measurements, parse large datasets, and generate validation reports.
• Run mixed-signal co-simulations (Cadence Virtuoso/Spectre) to verify connectivity and basic functionality of analog-digital interfaces.
• Collaborate with Design and Verification teams to debug silicon issues and correlate lab results with simulation data.

Skills & Qualifications

• Education: BSEE or MSEE with 3+ years of experience in IC modeling, design, or validation.
• Simulation Tools: Experience with Cadence Virtuoso, Spectre, or similar mixed-signal simulation environments.
• Modeling Languages: Proficiency in SystemVerilog (Real Number Modeling preferred) or Verilog-A.
• Test & Measurement: Hands-on experience with high-speed lab equipment for signal integrity and performance testing.
• Software/Scripting: Strong Python skills for automation (knowledge of libraries like NumPy, Matplotlib, or PyVISA is a plus).

Preferred Qualifications

• Familiarity with high-speed serial standards (e.g., SerDes, Ethernet, or PCIe).
• Experience working within a structured Product Development Process (PDP) in a large-scale semiconductor environment.
• Understanding of basic signal integrity concepts (jitter, eye diagrams, insertion loss).

Pay

The base salary range for this position is as mentioned below per year.

Benefits

We also provide competitive benefits, incentive compensation, and/or equity for certain roles. Company benefits include health. dental, and vision insurance. 401(k), and paid leave.