R&D Engineer IC Design

Responsibilities

• Create SystemVerilog-based verification environments (testbenches, checkers, transactors)
• Create and execute testplans for verifications of RTL and gatesim-based designs at both the block and chip level
• Create ATE testing vectors
• Create C-based diagnostic tests to be run on the actual silicon

Requirements

• A Master's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent
• A minimum of 6 years of work experience in Design Verification
• Strong knowledge and hands-on experience in verification methods, tools and environment
• Strong programming skills, including in System Verilog and scripts languages
• Knowledge and experience in UVM methodology is preferable
• Knowledge of networking and switching concept is a plus

Compensation and Benefits

• Annual base salary range: $108,000 - $172,800
• Discretionary annual bonus in accordance with relevant plan documents
• Equity in accordance with equity plan documents and equity award agreements
• Comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time
• The company follows all applicable laws for Paid Family Leave and other leaves of absence