Principal Test Engineer

Responsibilities

• Own test enablement for upcoming silicon projects, including ATE strategy, Advantest 93K hardware configuration, SmarTest 8 program structure, test flow development, debug visibility, datalogging, and manufacturing readiness.
• Drive first-silicon bring-up on ATE, including daily progress reporting, issue triage, silicon/ATE debug, characterization execution, correlation, and handoff from engineering bring-up to CP, FT, SLT, OSAT, and HVM release.
• Define and implement ATE characterization plans across voltage, frequency, temperature, process, functional content, HSIO margins, structural coverage, binning strategy, guardbands, and production limits.
• Develop and maintain ATE test methods, flows, revision-control framework, pattern conversion infrastructure, and production test content for functional, HSIO, ATPG/Scan, MBIST, PHY BIST, DC, leakage, IDDQ, and other manufacturing test types.
• Guide ATE test hardware development with vendors and OSATs, including wafer probe card, load board, socket, thermal control interface, tester resources, HSIO connectivity, signal integrity, power delivery, and active thermal management.
• Work with Design, DFT, Firmware, Product Engineering, third-party contractors, offshore teams, ATE suppliers, and OSATs to debug complex issues, improve test quality, close coverage gaps, and deliver production-ready test solutions on schedule.

Requirements

• 12+ years of experience in semiconductor manufacturing, ATE test development, product engineering, silicon bring-up, characterization, or production release for complex SoCs, CPUs, AI accelerators, chiplet-based devices, or advanced semiconductor products.
• Expert hands-on knowledge of Advantest 93K ATE test program development, including SmarTest 7 / SmarTest 8, tester hardware, digital patterns, test methods, test flow development, datalogging, debug flows, binning, revision control, and production integration.
• Strong experience in test architecture and HSIO test/debug, including PCIe, UCIe, DDR, SerDes, PHY BIST, protocol-based test, IO topology, bench-to-ATE correlation, oscilloscopes, BERTs, emulation, simulation, and production margining.
• A working understanding of functional testing, structural test integration, DFT concepts, PHY BIST, silicon fabrication process, packaging, product qualification, manufacturing steps, and HVM release requirements.
• Experience owning end-to-end project execution from architecture through first silicon, bring-up, characterization, CP/FT deployment, OSAT release, production ramp, yield debug, and continuous improvement.
• Strong ability to work across Design, DFT, Firmware, Product Engineering, vendors, OSATs, third-party teams, and customers, with proven debug capability across silicon, ATE hardware, SmarTest software, patterns, firmware, package/board design, HSIO IP, and manufacturing flows.

Qualifications

Please note that no relocation package is available for this role.

Skills

Salary Range $249,900-$338,100 per year

Benefits

We value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm.

Schedule

The total reward package will be shared with candidates during the recruitment and selection process.

Accommodations

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email Hybrid Working at Arm.

Equal Opportunities

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.