Principal Technology Development Engineer

About the role

Responsible for developing and maintaining MPS power IC devices and processes. This role involves process and device development for DMOS, Bipolar, CMOS, and high voltage devices, interfacing with various internal and external teams, and contributing to semiconductor device design and testing.

Responsibilities

• Process and device development for DMOS, Bipolar, CMOS, and high voltage devices.
• Interface with MPS Foundry Group and fabrication foundry personnel for development and qualification of devices, processes, and process changes.
• Define design rules for various analog process technologies and verify design rules vs. DRCs (Design Rule Checks) with the CAD group.
• Interface with the Design group to provide, clarify, and document device requirements and capabilities.
• Interface with the Mask Design Group and Mask Shop for device layout and mask/reticle tooling requirements.
• Interface and consult with Product Engineering and Foundry Group on yield questions.
• Engage in semiconductor device design to meet electrical specifications.
• Perform process and device simulation.
• Create test structure layout using CAD software.
• Define process experiments.
• Conduct electrical measurements at the wafer level.

Requirements

• MS or Ph.D. degree in Electrical Engineering or equivalent.
• 12+ years of overall experience in analog process and device development.
• 7+ years in development or transfer of BCD technologies.
• Familiarity with Bipolar, CMOS, DMOS, and high voltage devices.
• Knowledge of semiconductor device physics, process and device simulation, design rules, spice model extraction, graphics layout software, and mask making requirements.

Location

San Jose, CA

Pay

The base salary range for this position in San Jose, CA is $140,000 - $210,000, based on market location and factors including experience, skills, education, and other job-related reasons.