Principal Technical Engineer 3rd Party IP Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

What You Can Expect

• Assist Marvell in offering DDR/LPDDR/GDDR/HBM/eMMC memory interface cores to our clients.
• Create leading-edge designs for the latest applications in artificial intelligence, hyper-scaler, communications, and storage.
• Engage all parts of Marvell across all stages of SoC development including defining core requirements, validating IP developer competence, overseeing core development, technology compliance, core integration, test compliance and silicon validation.
• Aid sales in winning bids by working with leading edge IP providers to meet customer requirements.
• Manage 3rd party developers in completing core designs and providing required design rules.
• Advise the Marvell design center on core integration into custom silicon designs and hold joint reviews with the design center and 3rd party IP provider.
• Participate in post-silicon validation at customer sites, which may involve limited travel.
• Develop statements of work, lead provider progress reviews, and use 3rd party developer problem reporting tools to drive to problem resolution.
• Assist with 8D follow-through for significant supplier issues.

Qualifications

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree.
• Proficient in understanding of DDR type interfaces (DDR, LPDDR, GDDR, HBM, eMMC), including the challenges associated with SoC PHY integration, timing analysis, packaging, and multi-chip integrated packaging.
• Proficient in project management tasks required to manage 3rd party developers.
• Broad-based exposure to ASIC design flows required for releasing a chip to fabrication including logic synthesis, physical design, timing, DRC/LVS, Formal verification and electrical checking.
• Good understanding of Design-For-Test concepts including DFT logic insertion, test generation, scan and embedded core testing.
• Good communication and customer management skills.

Additional Information

Expected Base Pay Range (USD): $152,300 - $225,440, $ per annum. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements: Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.