Principal Technical Engineer 3rd Party IP Engineer

About the Role

As a Principal Technical Engineer (3rd Party IP Engineer) at Marvell, you’ll be part of the Central Engineering business group, the hub that provides IP to all other teams, including Storage, Security, and Networking. You’ll join the 3rd party IP management team, working alongside engineers to integrate subcontracted IP under the Marvell IP umbrella. This dynamic role engages all parts of Marvell and focuses on delivering DDR/LPDDR/GDDR/HBM/eMMC memory interface cores to clients in AI, hyperscale, communications, and storage markets.

You will be involved in all stages of SoC development: defining core requirements, validating IP developer competence, overseeing core development, ensuring technology compliance, core integration, test compliance, and silicon validation. You’ll assist sales in winning bids by collaborating with leading-edge IP providers to meet customer requirements, manage 3rd party developers, and advise Marvell design centers on core integration. Post-silicon validation may require limited travel.

Responsibilities

• Define core requirements for DDR/LPDDR/GDDR/HBM/eMMC memory interfaces.
• Validate IP developer competence and oversee core development.
• Ensure technology compliance, core integration, test compliance, and silicon validation.
• Assist sales in winning bids by working with IP providers to meet customer requirements.
• Manage 3rd party developers in completing core designs and providing required design rules.
• Advise Marvell design centers on core integration into custom silicon designs and conduct joint reviews with design centers and IP providers.
• Participate in post-silicon validation at customer sites (limited travel required).
• Develop statements of work and lead provider progress reviews.
• Use 3rd party developer problem reporting tools to drive issue resolution.
• Assist with 8D follow-through for significant supplier issues.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or related field with 5–10 years of professional experience, or Master’s degree and/or PhD with 3–5 years of experience, or equivalent professional experience in lieu of a formal degree.
• Proficiency in DDR-type interfaces (DDR, LPDDR, GDDR, HBM, eMMC), including challenges related to SoC PHY integration, timing analysis, packaging, and multi-chip integrated packaging.
• Experience with project management tasks required to manage 3rd party developers.
• Broad exposure to ASIC design flows, including logic synthesis, physical design, timing, DRC/LVS, formal verification, and electrical checking.
• Good understanding of Design-For-Test (DFT) concepts, including DFT logic insertion, test generation, scan, and embedded core testing.
• Strong communication and customer management skills.

Pay

Expected base pay range: $152,300 – $225,440 per annum. The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location, and market conditions.

Benefits

• Employee stock purchase plan with a 2-year look-back.
• Family support programs to help balance work and home life.
• Robust mental health resources to prioritize emotional well-being.
• Recognition and service awards to celebrate contributions and milestones.