Principal Silicon Technology Engineer

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. We’re looking for talent who want to leave the planet better than they found it—people who don’t shy away from humanity’s challenges but are determined to help solve them. AMD powers the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to technology that moves the world forward.

About the Role

We are seeking an exceptional Principal Engineer to serve as a technical authority and strategic contributor across the full product lifecycle of FPGA and ASIC solutions. This role encompasses advanced silicon technology evaluation, design enablement, process development, and manufacturing bring-up—spanning from early concept exploration through qualification and transfer to high-volume production (HVM).

Responsibilities

• Responsible for technology evaluation, design enablement, and process development of FPGA and ASIC products in advanced nodes.
• Responsible for product WAT analysis, performance correlation, and yield analysis during NPI in collaboration with foundry and design teams.
• Coordinate testchip design and tapeout for process and IP validation prior to NPI phase.
• Co-work with design, CAD, and PDK teams to accomplish robust IP and product designs.
• Assist silicon technology roadmap exploration to meet end customer requirements.

Requirements

• Familiar with advanced semiconductor technologies including FinFET, GAA, Backside Power, etc.
• Past experience supporting product silicon development and NPI is required.
• Strong background in development and tapeout of process and IP validation test vehicles.
• Working knowledge of IP and SoC analog and digital design flows with foundry PDK support experience.
• Experience with major EDA tools for device model, layout, circuit simulation, parasitic extraction, and physical verification.
• Familiarity with device reliability degradation mechanisms, test methods, and lifetime modeling.
• Working knowledge of 3DIC advanced packaging technologies including CoWoS and SoIC is a plus.
• Strong analytical, problem-solving, decision-making, and communication skills.
• Prior team leadership and management experience is a plus.

Qualifications

• Bachelor’s degree in engineering or physical science, preferably with an advanced degree (MS or PhD).

This role is not eligible for visa sponsorship.

Benefits

AMD offers a comprehensive benefits package. AMD benefits at a glance.