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Jobs · Information Technology · California

Principal Silicon Engineer

Microsoft · Mountain View, CA · 1 mo ago
HybridInformation Technology$143k–$275k/yrFull-time

Responsibilities

  • Design and verify PLL cores for custom SerDes interface IP
  • Architecture of the PLL core
  • Review timing reports of critical timing cells inside the PLL core (e.g., digital loop filters & analog-to-digital timing interfaces)
  • Simulation, post-layout verification & coordination with layout designers and other engineers on the macro
  • Global clock distribution owner responsible for low jitter clocking for high-speed clocking spines across the SerDes macro
  • Co-ordinate with modeling designers to ensure PLL functionality

Qualifications

  • Required Qualifications: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
  • Other Requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.

Preferred Qualifications

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience.
  • 1+ year(s) experience working on or leading projects from beginning-to-end.
  • 10+ years of experience in high-speed clocking and PLL design
  • Experience with deep sub-micron nodes and hands on layout optimization experience
  • Ability to review DV waveforms and debug calibration related issues
  • Post silicon validation Python, Perl & other scripting languages for post silicon validation
  • Matlab (Simulink) & modeling Analog Behavioural Modeling (ABM)

Pay

The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay.

Schedule

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Benefits

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances.

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