Principal RFIC Design Engineer - TeraWave
Applications will be accepted on an ongoing basis until the requisition is closed.
About the role
Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. This role represents an important addition to the Silicon Systems organization within the TeraWave team.
To further Blue Origin's mission of millions of people living and working in space for the benefit of Earth, we are bringing together technology from across our product lines to build the future of space-based communication. This role will be onsite in either the Bay Area-CA, San Diego-CA, Austin-TX, or Kent-WA. It is approved for a temporary remote work exception while specific sites are being developed.
Responsibilities
- Design and develop RFICs and mixed-signal ASICs
- Implement designs using Cadence Virtuoso, Spectre RF, and similar tools
- Develop analog models for verification methodologies for ASIC verification and requirements validation
- Create and execute test plans for pre- and post-silicon processes
- Conduct noise, linearity, power, mismatch, and other analog impairments implementation tradeoffs
- Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering
- Support lab integration and troubleshooting activities
- Resolve design and layout issues and drive solutions for interface timing, congestion, and other implementation challenges
- Adopt AI-based methodology throughout the design cycle of custom ICs, from design and simulation to verification, characterization, and manufacturing
Requirements
- 10+ years of industry experience in RFIC design and development, or the combination of industry experience and equivalent research from a PhD program
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline
- Experience with RF and/or mixed-signal block design
- Experience with Linux development environment
- Direct tape-out experience in taping out an RF or deep sub-micron analog mixed-signal chip
- Applicants must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum
Preferred Skills and Experience
- Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field
- Experience in full RF CMOS ASIC lifecycle (architecture, design, simulation, verification, validation, integration & test)
- Experience with Software-Defined Radio Architectures, ADC/DAC, and/or DSPs
- Knowledge of DSP and communications systems including spread spectrum, forward error correction, and modulation types (OFDM, QPSK, QAM, PCM/FM, PAM)
- Experience mentoring junior engineers
Pay
- For CA applicants: $213,331.00 - $298,663.05
- For WA applicants: $213,331.00 - $298,663.05
- Other site ranges may differ
Benefits
- Medical, dental, and vision insurance
- Basic and supplemental life insurance
- Paid parental leave
- Short- and long-term disability
- 401(k) with a company match of up to 5%
- Education Support Program
- Stock options for all regular employees (working at least 20 hours/week)
- Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays
- Dependent on role type and job level, employees may be eligible for additional benefits and bonuses based on individual contributions and company results
Bonus amounts and eligibility are not guaranteed and subject to change and cancellation.