Principal PLL IC Design Engineer - TeraWave

About the role

Blue Origin is seeking a Principal IC Design Engineer to lead the development of integrated Phase-Locked Loops (PLLs) and clocking systems in advanced CMOS/SiGe processes. This role is essential for advancing our technology offerings in space communication systems.

Responsibilities

• Leading the design, development and integration of PLLs and clock distribution in advanced CMOS FinFET and SiGe technologies, focusing on performance optimization and trade-off analysis.
• Utilizing full proficiency in Spectre and AMS flows to develop high-performance PLL circuits.
• Collaborating with RF and SOC system architects to define requirements for PLLs and their sub-blocks based on system specifications, ensuring seamless integration into RF payloads and terminals.
• Overseeing layout, top-level integration, floorplanning, and verification of the overall design for successful tape-out cycle.
• Working closely with validation and product engineers to develop test plans, facilitate bring-up, optimize performance, and ensure reliable & high-yield production cycles.
• Investigating and implementing fundamental analog building blocks to enhance overall circuit performance.
• Mentoring junior engineers for best design practices in analog domain.

Requirements

• Bachelor's degree in Electrical Engineering, or related technical discipline.
• 10+ years of experience in the design and development of high-speed (>20GHz) PLLs, and LO generation for high-performance applications at RF and mmWave frequencies.
• Proven expertise in loop design for phase noise/jitter, spur profile, area, and power optimization.
• Proficient in the design of PLLs and clock distribution circuits for wireless and wireline applications.
• Fundamental understanding of device physics for process selection and performance optimization.
• Full proficiency in mixed-mode and RF modeling, simulation, and verification methodologies using toolsets such as MATLAB, Spectre, SystemVerilog, and AMS.
• Extensive experience in PLL silicon characterization and debugging.
• Proficiency in the design of fundamental analog/RF building blocks, including amplifiers, filters, mixers, harmonic-rejection mixers, pre-scalers, and frequency multipliers.

Qualifications

• Advanced degree (MS/PhD) in Electrical Engineering or related field.
• Experience designing fractional-N PLLs, All-Digital PLLs (ADPLL) and/or sub-sampling PLLs is a plus.
• Extensive experience with fundamental analog building blocks such as LDOs, bias generators, and operational amplifiers.
• Familiarity with digital design, digital verification, and SystemVerilog modeling.

Skills

• Extensive experience in PLL silicon characterization and debugging.
• Proficiency in the design of fundamental analog/RF building blocks, including amplifiers, filters, mixers, harmonic-rejection mixers, pre-scalers, and frequency multipliers.
• Experience with clock domain synchronization techniques within systems involving multiple PLLs and/or clock domains.
• Full proficiency in mixed-mode and RF modeling, simulation, and verification methodologies using toolsets such as MATLAB, Spectre, SystemVerilog, and AMS.
• Advanced knowledge of Spectre and AMS flows.

Benefits

• Medical, dental, vision, basic and supplemental life insurance.
• Paid parental leave.
• Short and long-term disability.
• 401(k) with a company match of up to 5%.
• Education Support Program.
• Stock Options for all regular employees (working at least 20 hours/week).
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.