Principal PHY SerDes Validation Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

About the Role

The Marvell post silicon validation group designs and develops test platforms for validating multi-core Arm-based Network processors and custom ASIC’s, used in many communication infrastructure applications such as 5G base stations, NICs, Data Center and Cloud Computing platforms. The electrical characterization team is a post silicon validation sub-group focused on the debug and characterization of SERDES interfaces for various applications on the products. Characterization engineers are responsible for developing test platforms used and automated test suites to characterize the analog interfaces over process voltage and temperature (PVT) extremes to determine silicon viability for volume production.

Responsibilities

• Complete responsibility for PCIe or Ethernet PHY validation in a post-silicon environment.
• Define, document, execute, and report the overall PHY validation/test plan for Marvell storage devices.
• Lab-based silicon bring-up and unit test execution focused on Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the stack.
• Perform high-speed signal validation and analysis using various test equipment to measure Eye diagram / Jitter / BER.
• Analyze and debug issues on the PHY protocol of high-speed serial interfaces (PCIe or Ethernet).
• Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, and logic/protocol analyzers.
• Lead collaborative technical discussions to drive resolution on technical issues.
• Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to PCIe or Ethernet PHY.
• Work closely with customers to address design issues and debug failure cases.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or a related field and 10+ years of related professional experience, OR a Master’s degree and/or PhD in Computer Science, Electrical Engineering, or a related field with 3–5 years of experience.
• Strong understanding of high-speed SERDES, equalization techniques, and PCIe or Ethernet protocols.
• 5+ years of experience with High Speed IO testing, debugging, and validation.
• 5+ years of direct experience in SERDES characterization/design.
• In-depth knowledge of SERDES interfaces using NRZ or PAM4 signaling for PCIe or Ethernet interfaces; knowledge of relevant Ethernet standards (e.g., 10GbE, 100GbE, 400GbE) is a plus.
• In-depth working knowledge of test equipment used for SERDES characterization (scope, BERT, network analyzer, etc.).
• Deep understanding of high-speed electrical signaling principles, differential signaling, and mixed-signal designs.
• Experience in Python for automation framework development, as well as mathematical programming such as MATLAB.
• Critical thinking, a problem-solving attitude, and ownership of the group’s results.
• Knowledge of SERDES modeling techniques.
• Excellent verbal and written communication skills.

Qualifications

• Bachelor’s degree in Computer Science, Electrical Engineering, or a related field and 10+ years of related professional experience, OR a Master’s degree and/or PhD in Computer Science, Electrical Engineering, or a related field with 3–5 years of experience.
• Strong understanding of high-speed SERDES, equalization techniques, and PCIe or Ethernet protocols.
• 5+ years of experience with High Speed IO testing, debugging, and validation.
• 5+ years of direct experience in SERDES characterization/design.
• In-depth knowledge of SERDES interfaces using NRZ or PAM4 signaling for PCIe or Ethernet interfaces; knowledge of relevant Ethernet standards (e.g., 10GbE, 100GbE, 400GbE) is a plus.
• In-depth working knowledge of test equipment used for SERDES characterization (scope, BERT, network analyzer, etc.).
• Deep understanding of high-speed electrical signaling principles, differential signaling, and mixed-signal designs.
• Experience in Python for automation framework development, as well as mathematical programming such as MATLAB.
• Critical thinking, a problem-solving attitude, and ownership of the group’s results.
• Knowledge of SERDES modeling techniques.
• Excellent verbal and written communication skills.

Skills

• High-speed SERDES, equalization techniques, and PCIe or Ethernet protocols.
• Experience with High Speed IO testing, debugging, and validation.
• Direct experience in SERDES characterization/design.
• Knowledge of SERDES interfaces using NRZ or PAM4 signaling for PCIe or Ethernet interfaces.
• Working knowledge of test equipment used for SERDES characterization.
• Understanding of high-speed electrical signaling principles, differential signaling, and mixed-signal designs.
• Experience in Python for automation framework development, as well as mathematical programming such as MATLAB.
• Critical thinking and problem-solving skills.
• Knowledge of SERDES modeling techniques.
• Excellent verbal and written communication skills.

Benefits

• Employee Stock Purchase Plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental health resources to prioritize emotional well-being.
• A recognition and service awards to celebrate contributions and milestones.

Pay

Expected Base Pay Range (USD): 150,680 - 225,700, $ per annum

Schedule

Not specified