Principal Micro-architect, Coherent Interconnect

About the role

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world. Come build with us!

Responsibilities

• Lead the microarchitecture development of custom coherent interconnect IP and/or last-level cache (LLC) blocks for next-generation designs.
• Drive key aspects of coherent interconnect RTL design, including performance and power optimization, logic debug, and timing closure.
• Own the development and delivery of custom coherent interconnect IP and/or LLC blocks, ensuring high-quality execution and timely project completion.
• Collaborate closely with system architects to define and develop next-generation coherent interconnect and LLC architectures.
• Drive microarchitecture definition and specification, from early architectural exploration and microarchitectural research through detailed specification development and refinement.
• Partner with verification teams to ensure functional correctness and robust validation of the design.
• Develop high-quality RTL implementations that meet performance, power, and area (PPA) goals.
• Work with performance and power teams to optimize architecture and RTL implementations for efficiency and scalability.
• Collaborate with physical design and CAD teams to resolve implementation, timing, and integration challenges.
• Provide technical leadership and mentorship to junior engineers across the team.

Qualifications

• 15+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master’s degree, or 11+ years of experience with a PhD.
• Strong background driving RTL design of coherent interconnect and LLC sub-blocks for high-performance digital designs.
• Demonstrated experience spanning architecture definition through RTL implementation.
• Familiarity with on-chip network topologies such as mesh, ring, and crossbar interconnects, along with working knowledge of Arm AMBA5 CHI, AMBA4 ACE, AXI, and related coherent interconnect protocols.
• Deep expertise in Verilog/SystemVerilog and solid understanding of the complete ASIC design flow including STA, DFT, ECO flows, etc.
• Strong understanding of memory subsystem architecture, coherent cache design, system caches, coherency mechanisms, and directory-based snoop filter protocols.
• Proven experience leading technical initiatives, mentoring engineers, and collaborating effectively across dynamic, geographically distributed teams with strong communication and interpersonal skills.
• Experience with a scripting language like Perl or Python is a plus.

Pay

The base pay range for this role is between $221,700 and $364,800. Actual base pay will depend on variables that may include education, skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).

Benefits

• Medical, dental, vision, life insurance
• 401(k)
• Free onsite lunch
• Employee purchase program
• Tuition assistance (after 6 months)
• Paid time off
• Wellness incentives
• MBO bonus compensation (based on company, division, and individual performance)
• Potential eligibility for long term incentive plan and relocation