Principal Engineer DSP PHY Digital Design

About the role

As a Principal Engineer DSP PHY Digital Design in our Research & Development team, you'll shape the future of technology by architecting and simulating DSP signal chains for automotive Ethernet PHYs, driving groundbreaking projects, and bringing new ideas to life.

Responsibilities

• Architect and simulate DSP signal chains for automotive Ethernet PHYs: define features, performance targets, and algorithm specs for mixed-signal and digital teams
• Develop RTL design and verification for equalization and adaptation algorithms (e.g., FFE/DFE, adaptive filtering), including fixed-point considerations
• Design and implement timing recovery/synchronization blocks (CDR, tracking loops), addressing jitter tolerance and stability/latency tradeoffs
• Contribute to detection and coding/FEC integration: soft-information interfaces, performance/complexity tradeoffs, and link KPIs
• Build bit-true/fixed-point models and reference implementations primarily in C++ and MATLAB (Python optional)
• Define verification metrics and stress tests (BER/FER, convergence time, corner cases) and partner with DV to ensure coverage
• Support silicon bring-up and lab debug: correlate model ↔ silicon, root-cause issues, and iterate on algorithms/specs
• Collaborate across architecture, design, verification, and applications to deliver implementable and testable solutions

Requirements

• B.S. + 10 years (or M.S. + 7 years) in Electrical Engineering, Computer Engineering, or related field
• Strong fundamentals in digital communications and DSP, including probability/statistics
• Practical experience in high-speed wireline DSP, including some mix of: FFE/DFE, adaptation, CDR, MLSD/Viterbi concepts, FEC integration, fixed-point modeling
• Strong C++ and MATLAB skills for algorithm development, modeling, and analysis

Preferred Qualifications

• Experience with automotive Ethernet PHY/SerDes constraints (robustness, low latency, interoperability, EMI resilience)
• Familiarity with ADC-based receiver architectures and calibration concepts
• Experience translating algorithms into RTL-friendly specs (throughput/latency budgeting, memory/compute sizing, state-machine behavior)
• Knowledge of link startup/training/autoneg concepts and system validation
• Exposure to standards work (e.g., IEEE 802.3) or cross-company technical leadership