Principal Engineer, Digital Verification Engineering
Analog Devices · Chandler, AZ · 3 wk ago
Quality Assurance$11/hrFull-time
Key Responsibilities
- Drive adoption of AI/ML methodologies for failure clustering, regression triage, anomaly detection, and intelligent coverage optimization
- Define and own verification strategy, plans, and success metrics across block, top-level, and system contexts for mixed-signal ICs
- Build and scale mixed-signal verification infrastructure including reusable SystemVerilog/UVM testbenches, monitors, scoreboards, and automated checkers
- Lead functional coverage planning, closure analysis, and sign-off for tape-out readiness
- Drive silicon correlation by comparing simulation expectations against lab measurements, refining models and tests based on measured behavior
- Lead verification architecture and methodology reviews, influencing best practices across projects
- Collaborate with design, applications, and test teams to ensure verification reflects real use-cases, operating modes, and corner scenarios
Required Skills And Experience
- MSEE or MSCE with 10+ years of IC verification experience, or PhD with 8+ years (BSEE/BSCE with equivalent depth considered)
- Expert-level proficiency in SystemVerilog and UVM with a track record of building coverage-driven verification environments for mixed-signal products
- Track record of owning end-to-end verification readiness from planning through tape-out sign-off and production release
- Strong Python scripting skills with experience applying AI/ML techniques to enhance verification productivity
- Deep knowledge of formal verification, assertion-based methodology, and clock domain crossing analysis
- Proficiency with Cadence verification tools: Xcelium (simulation), JasperGold (formal verification)
- Excellent presentation, technical writing, and communication skills
Preferred Qualifications
- Experience with mixed-signal and AMS verification techniques including Verilog-AMS, real-number modeling, and behavioral abstraction
- Experience with gate-level simulation, SDF back-annotation, and post-layout verification
- Background verifying power management and interface-rich mixed-signal devices across multiple power domains
- Strong analytical and problem-solving abilities
- Able to work effectively in a collaborative team environment