Principal Engineer - Design For Test (DFT)

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As a Digital IC Design Principal Engineer with Marvell, you’ll be a member of the Custom Silicon Engineering team. This team is a leader in large multi-die designs that drive high compute performance and acceleration in many markets, including custom AI, 5G and 6G. The role will be challenging and will require an experienced DFT engineer that can work with existing DFT solutions while also creating new solutions to address industry first issues.

What You Can Expect

• Implement DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs
• Run Tessent tools for insertion of all DFT structures
• Work with chiplet DFT solutions, including Tessent SSN
• Show proficiency in ICL/PDL, PTAP/STAP, 1687
• Show instrument-level access inside a chip
• Help with Design-for-Test architecture definition and implementation of additional DFT/DFX features
• Define STA constraint, generate patterns, and perform post-silicon bring-up and debug
• Grow to include mentoring, guiding, and driving a small team of DFT engineers
• Enhance DFT methodologies and tools

What We're Looking For

• Bachelor’s, Master’s degree or PhD in Computer Science, Electrical Engineering or related fields with minimum of 10 years of work experience
• Direct DFT experience with at least 8 years in the custom chip (ASIC) design business
• Hands-on working experience in various stages of DFT-Execution: SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bring-up/Debug
• Thorough knowledge on various DFT/Test architecture solutions for 2.5D/3D IC design
• Strong fundamentals in digital circuit design and logic design
• Understanding of DFT flows and methodologies and experience with Siemens/Synopsys Tool set (Tessent, Spyglass/Tmax, Genus, Modus, NCSim/DC), with Tessent the EDA tool flow in use
• Proven track record of problem solving and innovation to meet challenging design requirements
• Excellent team player and can work with different function leaders, across different geographies to define and execute the DFT project to completion
• Excellent communications skills both verbal and written
• Scripting skills using Python, PERL, Tcl and C-Shell is plus

Expected Base Pay Range (USD)

$160,400 - $237,320, $ per annum

Additional Compensation and Benefit Elements

• Employee stock purchase plan with a 2-year look back
• Family support programs to help balance work and home life
• Robust mental health resources to prioritize emotional well-being
• A recognition and service awards to celebrate contributions and milestones

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.