Principal Engineer - CAD, SoC Floorplan and Advance Technode

About the role

As part of the Solutions Engineering CAD team, you will drive next-generation floor-planning, power delivery network (PDN) methodologies, and technology-node-aware implementation solutions for high-performance and low-power designs. You will work closely with architecture, RTL, IP, physical design, and package-board teams to optimize SoC and multi-die implementations across advanced technology nodes.

Responsibilities

• Develop and drive advanced SoC floor-planning methodologies for complex hierarchical and multi-die designs.
• Define and optimize power delivery network (PDN) implementation for advanced-node implementation, including IR/EM-aware planning and power integrity optimization.
• Build scalable automation and methodologies for top level floor-planning, power mesh and clocking, hierarchical subsystems, IO and IP integration, routing resource congestion analysis, and technology-node-aware implementation flows.
• Drive methodology innovations for advanced technology nodes, ultra-low voltage designs, and chiplet/multi-die systems.

Required Skills and Experience

• Strong expertise in SoC design flow automation for hierarchical floor-planning, PDN design, and advanced physical implementation methodologies.
• Solid programming and scripting skills, including Python, C, EDA tools, version control systems (Git), and distributed processing/debug environments.
• Hands-on experience with low-power design methodologies, UPF-based design, chip finishing, and physical verification flows in advanced process technologies.
• Excellent problem-solving, communication, and collaboration skills, with the ability to work effectively across globally distributed teams.
• Proven ability to lead technical initiatives and collaborate with internal engineering teams, foundries, and ecosystem partners.

Nice to Have Skills and Experience

• Deep understanding of advanced clocking structures, power delivery optimization, and physical verification convergence techniques.
• Familiarity with AI-assisted design automation and methodology optimization flows.