Jobs · Engineering · California

Principal Engineer, AI & ML Design Verification (AI2517)

SiMa.ai · San Jose, CA · 2 mo ago
Engineering$204k–$316k/yrFull-time

About the role

The Design Verification (DV) team at SiMa is involved in the functional verification of Machine Learning Accelerator (MLA) and data processing at block, sub-system and SoC levels. This role also involves bring-up and debugging on emulators and silicon.

Responsibilities

  • Independently perform MLA verification execution and closure.
  • Participate in MLA architecture, micro-architecture and feature discussions and reviews.
  • Define and develop MLA test bench components using UVM & System Verilog.
  • Develop and execute test plans.
  • Lead code coverage reviews and closure.
  • System Verilog Assertion functional coverage development and closure.
  • Manage debugging of test and regression failures.
  • Work closely with the Architecture, SoC Hardware and Software teams.

Requirements

  • BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification of pipeline-based designs, preferably MLAs, DSPs, CPUs or GPUs.
  • Very good experience of UVM and System Verilog based verification methodology is a must.
  • Good working experience of development of UVM and System Verilog Test Bench (BFMs, ScoreBoards, SVA etc..) from scratch along with usage know-how of debug & coverage tools.
  • Skill set for silicon debug on the lab/board set-up is a plus.
  • Good debug, coding and problem-solving skills.
  • Knowledge of AMBA protocols is a must.
  • Formal/SVA knowledge is a plus.

Qualifications

  • Can-do attitude.
  • Strong team player.
  • Curious, creative and good at solving problems.
  • Execution and results-oriented.
  • Self-driven, thinks big and is highly accountable.
  • Good communication skills.

Skills

  • UVM and System Verilog based verification methodology.
  • Development of UVM and System Verilog Test Bench (BFMs, ScoreBoards, SVA etc..).
  • Debugging and coverage tools.
  • Debugging on the lab/board set-up.
  • Formal/SVA knowledge.

Benefits

  • Annual salary range: $203,800 - $315,900.
  • Eligible for private company equity.
  • A comprehensive package of employee benefits.

Pay

The annual salary for this position ranges from $203,800 - $315,900. The actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs.

Schedule

This position requires a full-time, on-site presence in our San Jose, CA office.

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