Staff Design Verification Engineer (AI/ML)

About the role

As a Staff Design Verification Engineer, you will develop and execute verification strategies for complex analog and mixed-signal ICs, from test planning through coverage closure. You will apply AI/ML techniques to improve regression efficiency, debug throughput, and coverage analysis. Your work will contribute to product quality and delivery across multiple business units, ensuring ADI's next-generation mixed-signal and power management products meet rigorous quality standards.

Key Responsibilities

• Apply AI/ML methodologies for failure clustering, regression triage, anomaly detection, and coverage optimization
• Develop and execute verification plans, defining coverage models and success metrics for mixed-signal IC blocks and subsystems
• Build and maintain SystemVerilog/UVM testbenches, monitors, scoreboards, and automated checkers for mixed-signal verification
• Perform functional coverage analysis and drive coverage closure toward tape-out readiness
• Support silicon correlation by comparing simulation expectations against lab measurements and refining tests based on results
• Participate in verification reviews, contributing technical analysis on coverage completeness and methodology improvements
• Collaborate with design, applications, and test teams to ensure verification reflects real use-cases and operating conditions

Required Skills and Experience

• MSEE or MSCE with 7+ years of IC verification experience, or PhD with 5+ years (BSEE/BSCE with equivalent depth considered)
• Strong proficiency in SystemVerilog and UVM with experience building coverage-driven verification environments for mixed-signal products
• Demonstrated ability to deliver verification through tape-out sign-off and production release
• Solid Python scripting skills with experience applying AI/ML techniques to enhance verification productivity
• Knowledge of formal verification, assertion-based methodology, and clock domain crossing analysis
• Proficiency with Cadence verification tools: Xcelium (simulation), JasperGold (formal verification)
• Excellent presentation, technical writing, and communication skills

Preferred Qualifications

• Curiosity and initiative to explore AI/ML techniques and emerging tools that can transform verification workflows, with an enthusiasm for discovering more effective ways of working
• Experience with mixed-signal and AMS verification techniques including Verilog-AMS, real-number modeling, and behavioral abstraction
• Experience with gate-level simulation, SDF back-annotation, and post-layout verification
• Strong analytical and problem-solving abilities
• Ability to work effectively in a collaborative team environment