Principal Design Engineer

About the role

Team Credo is seeking a principal technical leader to drive both hands-on digital ASIC design and strategic architecture direction for our High-Performance Network Interface IP portfolio. This role has direct impact on the interconnect infrastructure enabling next-generation AI and HPC systems. Depending on the candidate's strengths, the focus may span from leading RTL development and design execution to shaping product roadmaps, architecture requirements, and long-range technology investments. The ideal candidate brings deep expertise in computing and communication systems — including memory subsystems, inter- and intra-chip interconnects, Ethernet, CXL, PCIe, UCIe, and UALink — and understands how these technologies support scalable AI infrastructure across accelerator, chiplet, and data center environments.

Why Credo

• Purpose: We invest in what matters. From meaningful future-shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
• People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
• Possibilities: Our belief shapes what's next. Our technology powers the most reliable and energy-efficient connections around the world — and our team powers new products and markets that come next.

About Credo

Credo's mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI. Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.

Responsibilities

• Lead technical evaluations of RFQs and guide functionality, power, performance, and area tradeoffs; partner with product marketing and key customers to define best-in-class technical solutions across product generations.
• Help define product and technology roadmaps based on customer needs, market direction, and technical trends; translate standards, constraints, and ecosystem trends into architecture goals, requirements, and engineering priorities.
• Own the scoping, planning, and execution tracking of design activities and product releases; guide architectural decisions with a focus on outcomes, scalability, product impact, and efficient implementation; create clear documentation, including functional specifications, architecture, microarchitecture, and product requirements.
• Develop, debug, and enhance RTL, running lint checks and simulation; perform synthesis tasks (timing constraints, logic synthesis, report analysis, timing closure, ECOs); partner with verification to shape test plans, review results, and drive root-cause analysis and resolution of failures; lead and contribute to design reviews for technical rigor and design quality.
• Identify risks, dependencies, and roadmap gaps early and drive cross-team mitigation; align engineering, product, and business teams on customer needs, differentiation, and execution; communicate technical strategy, priorities, and rationale to internal and external stakeholders.

Qualifications

Basic Qualifications

• Eight or more years of experience, with a bachelor's or master's degree in electrical engineering, computer engineering, or a related field, and a strong track record of technical leadership, including the ability to plan, manage, and influence engineering, product, and business stakeholders.
• Digital design expertise (state machines, data paths, FIFOs, asynchronous crossings, clock and reset concepts, high-speed and low-power design) using Verilog/SystemVerilog and synthesizable design concepts targeting deep sub-micron nodes, with a comprehensive understanding of architectural impact on logic synthesis, timing closure, and physical implementation.
• Deep knowledge of networking protocols (802.3 Ethernet, PCIe, CXL, UCIe, UALink, and related standards), inter- and intra-chip buses and fabrics (NoC, coherent/non-coherent fabrics, arbitration, flow control, latency/bandwidth optimization), and FEC algorithm theory and basic data communication theory.
• Systems thinking to evaluate technical tradeoffs and translate them into product direction and prioritized requirements, with excellent communication skills for presenting complex concepts, driving alignment, and producing clear requirements and strategy documents.
• Advanced debugging skills and Unix/Linux scripting (Perl, Tcl, Python, shell), with experience using Cadence, Mentor, and Synopsys tools for simulation, lint, and synthesis.

Preferred Qualifications

• AI infrastructure or AI workload knowledge
• UVM and constrained-random testing experience

Pay

Base salary range: $144,000 – $228,000 per year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity, and a full range of medical and other benefits.