Principal ASIC Design Engineer

About the role

At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing. Micron’s Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. A core part of that work is silicon-based validation of novel PHY solutions, and we are growing the team to execute. As the Principal ASIC Design Engineer, you will be the primary digital contributor on a deliberately small, senior team — united around the goal of carrying high-speed interface technologies from architecture to tape-out. The team’s analog and chip-level architecture is anchored by a deeply experienced analog custom design engineer; your role is to be the authoritative digital voice — owning RTL design and micro-architecture of the digital blocks, defining timing constraints, supporting verification, and serving as the key interface between the digital design and the analog and layout specialists who will carry the implementation through to silicon. On a test ASIC of this scope, the front-end digital work is the critical path, with contractor and layout support engaged as bandwidth demands warrant.

Responsibilities

• Own the micro-architecture and RTL implementation of all digital soft IP blocks — CSR/register file, clocking control logic, management bus interfaces, and control state machines — in synthesizable SystemVerilog. Define and document block-level architecture specifications and interface control documents; serve as the authoritative reference for digital design intent. Define CDC strategy for digital blocks and ensure clean closure using standard analysis tools. Coordinate with the analog design lead on top-level chip integration, analog/digital partitioning, and chip boundary interface definitions.
• Execute logic synthesis (Synopsys Design Compiler or Cadence Genus) and drive optimization toward PPA targets. Develop and maintain block-level SDC constraints; execute and close static timing analysis (PrimeTime or Tempus) across required corners and modes.
• Serve as the primary digital interface to the layout and implementation team — providing synthesized netlists, SDC constraints, floorplan guidance, and design intent documentation to enable effective physical implementation. Review and provide feedback on floorplan decisions, placement constraints, and timing closure results; partner with layout specialists to resolve implementation issues rooted in RTL or constraints. Coordinate with the verification team on scan chain insertion, DFT strategy, and ATPG planning. Where bandwidth and experience allow, participate directly