Principal ASIC Design Engineer

About the role

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing. Micron’s Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. A core part of that work is silicon-based validation of novel PHY solutions, and we are growing the team to execute.

Responsibilities

• Digital Block Architecture & RTL Design: Own the micro-architecture and RTL implementation of all digital soft IP blocks — CSR/register file, clocking control logic, management bus interfaces, and control state machines — in synthesizable SystemVerilog. Define and document block-level architecture specifications and interface control documents; serve as the authoritative reference for digital design intent. Define CDC strategy for digital blocks and ensure clean closure using standard analysis tools. Coordinate with the analog design lead on top-level chip integration, analog/digital partitioning, and chip boundary interface definitions.
• Synthesis & Timing: Execute logic synthesis (Synopsys Design Compiler or Cadence Genus) and drive optimization toward PPA targets. Develop and maintain block-level SDC constraints; execute and close static timing analysis (PrimeTime or Tempus) across required corners and modes.
• Physical Design Interface: Serve as the primary digital interface to the layout and implementation team — providing synthesized netlists, SDC constraints, floorplan guidance, and design intent documentation to enable effective physical implementation. Review and provide feedback on floorplan decisions, placement constraints, and timing closure results; partner with layout specialists to resolve implementation issues rooted in RTL or constraints. Coordinate with the verification team on scan chain insertion, DFT strategy, and ATPG planning. Where bandwidth and experience allow, participate directly in place-and-route and physical verification flows.
• Self-Verification & Verification Support: Self-verify RTL through block-level simulation (VCS or Xcelium), waveform debug (Verdi or DVE), and directed testing before engaging the verification team. Write SystemVerilog Assertions (SVA) for critical control sequences and protocol compliance. Collaborate with the Design Verification Engineer on the block-level verification plan, testbench coverage, and bug resolution. Support GLS and timing simulation using released netlists and SPF/parasitics; assist lab bring-up with simulation waveforms and register-level debug.
• Documentation: Maintain block specifications, SDC rationale, implementation guidance, and ECO history as institutional knowledge for follow-on chip development.

Requirements

Required

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
• 7–12 years of ASIC design experience with at least one complete front-to-back tape-out
• Proficiency in synthesizable SystemVerilog RTL design — linting-clean, well-documented coding practices
• Hands-on experience with logic synthesis (Design Compiler or Genus) and static timing analysis (PrimeTime or Tempus)
• Proficiency with RTL simulation and debug tools (VCS or Xcelium; Verdi or DVE) for block-level self-verification
• Solid understanding of CDC analysis methodologies (SpyGlass, JasperGold CDC, or equivalent)
• Ability to work effectively at