Principal Analog Design Engineer

About the Role

As an Analog Design Engineer at Tylsemi, you will design and deliver high-performance analog and mixed-signal circuits that enable robust, manufacturable silicon. This role spans a wide experience range (5–30 years) and is ideal for engineers who combine strong fundamentals with practical execution—translating system requirements into silicon-ready designs, validating performance across corners, and partnering closely with layout, verification, test, and product teams to drive first-time-right outcomes.

Responsibilities

• Own end-to-end analog block development: requirements definition, architecture, transistor-level design, simulation, and signoff
• Design and optimize analog/mixed-signal circuits such as amplifiers, references, biasing, regulators (LDO/DC-DC support), comparators, oscillators/clocking, data converters (as applicable), and sensor/AFE front ends
• Drive performance across PVT corners, mismatch/Monte Carlo, aging/reliability considerations, and realistic loading/interaction with surrounding blocks
• Partner with layout to guide floorplanning, matching/guarding strategies, parasitic-aware design, and post-layout closure (PEX)
• Develop and maintain testbenches, modeling collateral, and documentation to enable efficient verification and integration
• Support silicon bring-up and debug: correlate lab data to simulations, root-cause issues, and implement design fixes or ECOs
• Collaborate cross-functionally with digital, firmware, DFT, validation, and product engineering to ensure system-level success
• Contribute to design methodology improvements: reusable circuits, checklists, signoff flows, and best practices that scale across programs

Requirements

• 5+ years of experience in analog or mixed-signal IC design (scope and ownership aligned to experience level)
• Strong fundamentals in analog circuit design, device physics, noise, stability/compensation, and feedback systems
• Proficiency with industry-standard EDA tools and simulation flows (e.g., Spectre/HSPICE, ADE, waveform/debug tooling)
• Experience closing designs through post-layout parasitics and across process/voltage/temperature corners
• Ability to translate ambiguous system needs into clear block requirements and executable design plans
• Strong debugging skills and comfort working with lab/validation teams to correlate silicon to simulation
• Clear communication and high ownership in cross-site, cross-functional environments

Nice to Have

• Experience with high-speed or precision analog (low-noise, low-offset, high-linearity) depending on product needs
• Background in power management (LDOs, bandgaps, references, protection, start-up, transient response)
• ADC/DAC, power-related analog experience
• Familiarity with reliability/ESD considerations and design-for-manufacturability practices
• Experience supporting production ramp: yield learning, characterization, and test correlation
• Success in roles where analog blocks meet spec with margin across PVT, mismatch, and post-layout effects

About Tylsemi, Inc.

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That's what we solve. Tylsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale. This isn't a nice-to-have. It's the critical path.

Culture & Team

• No Politics, No Bureaucracy: There are no layers, no approval chains, no corporate theater. If you have an idea, we test it. If it works, we ship it. No endless meetings, no PowerPoint presentations to convince middle management.
• Remote-Friendly, Global Team: US team: Bay Area preferred, but we hire the best people regardless of location. India team: Building a world-class design center in Bangalore.
• Move Fast, Ship Real Products: We're not a research project. We have paying customers, committed capital, and aggressive timelines. This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

Pay

The pay range for this role is $175,000 - $350,000 USD per year (San Jose HQ).