Pre-si Power and Performance System Validation Engineer
for sections: About the sections we include. Must not repeat job title. Must not include Job ID etc. Must include only sections with real content. Must not include boilerplate like EEO, legal, etc. Must not include duplicated lines. Must not include cookie/navigation etc.
We need to parse the job description and extract relevant content: About the role? The posting includes "Life at Intel" and "The Role and Impact". Also "Business Group". Then "Key Responsibilities". Then "Well Qualified Candidates Should Possess The Following Behavioral Traits". Then "Qualifications" with subparts: Education, Experience, Technical Skills, How To Stand Out (Preferred Qualifications). Then "Benefits". Then "Job Type Experienced Hire Shift Shift 1 (United States of America)" maybe schedule? Actually shift is given: Shift 1 (United States of America). Also location details. Also "Annual Salary Range". Also "Work Model for this Role". So we need sections: About the role (maybe combine Life at Intel and The Role and Impact?), Responsibilities, Requirements (or Qualifications), Benefits, Pay, Schedule. We need to decide which sections to include based on content.
We must not create sections with placeholder text. So we need actual content.
Let's extract:
- About the role: Could be "Life at Intel" paragraph: "Intel is shaping the future of technology..." plus "The Role and Impact" paragraph describing role. Could combine into About the role.
- Responsibilities: The list under "Key Responsibilities". Those are bullet points.
- Requirements/Qualifications: The "Well Qualified Candidates Should Possess The Following Behavioral Traits" (behavioral traits) plus "Qualifications" section (Education, Experience, Technical Skills, Preferred Qualifications). Could combine into Requirements.
- Benefits: The "Benefits At Intel" paragraph plus maybe "We offer a total compensation package..." later. Also "Annual Salary Range" is Pay. So Benefits section should include description of benefits (health, retirement, vacation, etc). The posting includes: "Benefits At Intel Our total rewards package goes above and beyond just a paycheck... Go to Intel Benefits | Intel Careers for details...". Also later: "We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation." So we can include that.
- Pay: The "Annual Salary Range for jobs which could be performed in the US: $122,440.00 - 232,190.00 USD". Also mention that individual pay determined by location etc. So we can include Pay section with that range.
- Schedule: The posting includes "Job Type Experienced Hire Shift Shift 1 (United States of America)" and "Work Model for this Role This role will require an on-site presence." So schedule could be shift and work model. We can include Schedule section with shift and work model.
We must not include duplicated lines. Also must not include boilerplate like EEO, N/A, etc. Must not include "Posting Statement", "Position of Trust N/A", "ADDITIONAL INFORMATION". Also must not include "How To Stand Out (Preferred Qualifications)" as a separate heading? It could be part of Qualifications.
We need to output only HTML fragment, no or . Use for section headings. Use - for any list of duties/requirements/benefits. Use
for prose.
We need to preserve all substantive information; do not invent or summarize away detail. So we need to include all details from the sections we include.
Let's craft sections:
About the role
Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone.
As a SoC Power Thermal Performance Validation and Optimization Engineer, you will play an essential role in ensuring Intel's products achieve optimal power, thermal, and performance benchmarks at the system-on-chip (SoC) level. In this position, you will develop and execute validation methodologies, optimize hardware/software solutions, and perform SoC-level debugging to address power, thermal, and performance challenges. Your contribution will directly impact Intel's ability to deliver competitive, high-performing products to market. This role is part of Intel's Data Center Group (DCG), which focuses on designing innovative solutions to power the next generation of computing platforms for data centers. As a member of the PTP PreSi Correlation Solution team, you will contribute to shaping the development and validation processes for cutting-edge technologies, ensuring Intel meets and exceeds industry standards for performance and efficiency.
That seems good.
Responsibilities
- Develop and execute SoC-level power, thermal, and performance validation and optimization plans across Intel products.
- Collaborate with architecture, design, firmware, and software teams to ensure power, thermal, and performance meet competitive targets and specifications.
- Establish and execute methodologies for validating hardware/software optimizations and ensure alignment with business KPIs.
- Perform SoC-level debug to identify root causes and resolve functional and triage failures related to power, thermal, and performance.
- Configure and set up data loggers to collect and analyze thermal data.
- Develop and maintain validation infrastructure, including performance monitors, behavioral checkers, and testing environments.
- Produce comprehensive validation reports summarizing activities and results, and communicate findings effectively to relevant teams.
- Drive continuous improvements to validation strategies, methodologies, and processes.
Requirements
We need to include behavioral traits, qualifications (education, experience, technical skills, preferred qualifications). We'll need to format as prose or lists.
We could have subheadings? But only allowed for section headings. We could still use
and
inside.
We'll include:
Behavioral Traits: Strong analytical and problem-solving aptitude. Effective communication and documentation skills for cross-functional collaboration. Ability to work across team in multi-faceted groups (architecture, design, verification, firmware, software, and platform teams.)
Then Education:
Education (Minimum Qualifications): Bachelors in electrical, Computer Engineering, or related field. A master's degree is preferred.
Experience:
Experience: 3+ years of experience in SoC power and performance validation. 3+ years of experience in Pre-Si simulation and emulation. 3+ years of experience developing and/or optimization of power/performance KPI's.
Technical Skills (2+ Years each):
We could list as .
Technical Skills (2+ Years of experience in each):
- Debugging experience for SoC-level power, thermal, and performance failures.
- Knowledge of hardware/software optimizations for power and performance.
- Experience of silicon verification, test program development and test plan execution.
- Knowledge of RTL language, in-circuit emulation and FPGA fast prototyping is an advantage.
- Experience with Python Programming language.
Preferred Qualifications (How To Stand Out):
We could list as with heading.
Preferred Qualifications:
- Graduate degree (Masters or PhD).
- Knowledge of DSP, ETHERNET, and 3G/4G/5G.
- 2+ years' experience in SoC FPGA/Emulation function.
- 2+ years' experience with System (SoC) level debug using JTAG debuggers.
- 1+ year experience in Pre-Si functional design, validation, and/or HW/FW/SW integration.
- 1+ year experience on major Pre-Si platforms: logic simulation, virtual platform, FPGA, and/or emulation.
- Expertise in system-level power management of real-time processors and systems.
- Understand MIPI MPHY, JTAG, DDR, PCIe/USB/PCI-E/ETHERNET/SPMI bus protocol.
- Familiarity with validation tools such as data loggers, behavioral checkers, and state space coverage techniques.
- Familiar with system board design/debugging and usage of lab equipment like Oscilloscope and Logic analyzer.
- Knowledge of AI accelerators systems including GFX, NPU, NPP design and architecture.
- Experience with performance modeling, benchmarking, and validation infrastructure setup.
- Debugging experience for SoC-level power, thermal, and performance failures.
- Familiarity with validation tools such as data loggers, behavioral checkers, and state space coverage techniques.
- Knowledge of hardware/software optimizations for power and performance.
Note there are duplicates in preferred qualifications (some repeated). We should preserve all substantive information but avoid duplication? The instruction: "Preserve ALL substantive information; do NOT invent or summarize away detail." It doesn't say to deduplicate. However duplicates may be considered boilerplate? They are repeated lines in the original. Might be okay to keep but could be considered duplicated lines. The instruction also says: "Remove cookie/navigation/legal/EEO/equal-opportunity/scam-warning boilerplate, duplicated lines, and application instructions." So we should remove duplicated lines. So we need to deduplicate the preferred qualifications list. Let's identify duplicates:
- "Debugging experience for SoC-level power, thermal, and performance failures." appears twice.
- "Familiarity with validation tools such as data loggers, behavioral checkers, and state space coverage techniques." appears twice.
- "Knowledge of hardware/software optimizations for power and performance." appears twice.
We should keep only one instance each.
Thus we will produce a deduplicated list.
Let's compile unique items:
1. Graduate degree (Masters or PhD).
2. Knowledge of DSP, ETHERNET, and 3G/4G/5G.
3. 2+ years' experience in SoC FPGA/Emulation function.
4. 2+ years' experience with System (SoC) level debug using JTAG debuggers.
5. 1+ year experience in Pre-Si functional design, validation, and/or HW/FW/SW integration.
6. 1+ year experience on major Pre-Si platforms: logic simulation, virtual platform, FPGA, and/or emulation.
7. Expertise in system-level power management of real-time processors and systems.
8. Understand MIPI MPHY, JTAG, DDR, PCIe/USB/PCI-E/ETHERNET/SPMI bus protocol.
9. Familiarity with validation tools such as data loggers, behavioral checkers, and state space coverage techniques.
10. Familiar with system board design/debugging and usage of lab equipment like Oscilloscope and Logic analyzer.
11. Knowledge of AI accelerators systems including GFX, NPU, NPP design and architecture.
12. Experience with performance modeling, benchmarking, and validation infrastructure setup.
That's 12 items.
Now Benefits section:
We have two paragraphs: "Benefits At Intel Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion
- for any list of duties/requirements/benefits. Use
for prose. We need to preserve all substantive information; do not invent or summarize away detail. So we need to include all details from the sections we include. Let's craft sections:
About the role
Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone.
As a SoC Power Thermal Performance Validation and Optimization Engineer, you will play an essential role in ensuring Intel's products achieve optimal power, thermal, and performance benchmarks at the system-on-chip (SoC) level. In this position, you will develop and execute validation methodologies, optimize hardware/software solutions, and perform SoC-level debugging to address power, thermal, and performance challenges. Your contribution will directly impact Intel's ability to deliver competitive, high-performing products to market. This role is part of Intel's Data Center Group (DCG), which focuses on designing innovative solutions to power the next generation of computing platforms for data centers. As a member of the PTP PreSi Correlation Solution team, you will contribute to shaping the development and validation processes for cutting-edge technologies, ensuring Intel meets and exceeds industry standards for performance and efficiency.
That seems good.Responsibilities
- Develop and execute SoC-level power, thermal, and performance validation and optimization plans across Intel products.
- Collaborate with architecture, design, firmware, and software teams to ensure power, thermal, and performance meet competitive targets and specifications.
- Establish and execute methodologies for validating hardware/software optimizations and ensure alignment with business KPIs.
- Perform SoC-level debug to identify root causes and resolve functional and triage failures related to power, thermal, and performance.
- Configure and set up data loggers to collect and analyze thermal data.
- Develop and maintain validation infrastructure, including performance monitors, behavioral checkers, and testing environments.
- Produce comprehensive validation reports summarizing activities and results, and communicate findings effectively to relevant teams.
- Drive continuous improvements to validation strategies, methodologies, and processes.
Requirements
We need to include behavioral traits, qualifications (education, experience, technical skills, preferred qualifications). We'll need to format as prose or lists. We could have subheadings? But onlyallowed for section headings. We could still use
and
- inside.
We'll include:
- Debugging experience for SoC-level power, thermal, and performance failures.
- Knowledge of hardware/software optimizations for power and performance.
- Experience of silicon verification, test program development and test plan execution.
- Knowledge of RTL language, in-circuit emulation and FPGA fast prototyping is an advantage.
- Experience with Python Programming language.
- Graduate degree (Masters or PhD).
- Knowledge of DSP, ETHERNET, and 3G/4G/5G.
- 2+ years' experience in SoC FPGA/Emulation function.
- 2+ years' experience with System (SoC) level debug using JTAG debuggers.
- 1+ year experience in Pre-Si functional design, validation, and/or HW/FW/SW integration.
- 1+ year experience on major Pre-Si platforms: logic simulation, virtual platform, FPGA, and/or emulation.
- Expertise in system-level power management of real-time processors and systems.
- Understand MIPI MPHY, JTAG, DDR, PCIe/USB/PCI-E/ETHERNET/SPMI bus protocol.
- Familiarity with validation tools such as data loggers, behavioral checkers, and state space coverage techniques.
- Familiar with system board design/debugging and usage of lab equipment like Oscilloscope and Logic analyzer.
- Knowledge of AI accelerators systems including GFX, NPU, NPP design and architecture.
- Experience with performance modeling, benchmarking, and validation infrastructure setup.
- Debugging experience for SoC-level power, thermal, and performance failures.
- Familiarity with validation tools such as data loggers, behavioral checkers, and state space coverage techniques.
- Knowledge of hardware/software optimizations for power and performance.
Behavioral Traits: Strong analytical and problem-solving aptitude. Effective communication and documentation skills for cross-functional collaboration. Ability to work across team in multi-faceted groups (architecture, design, verification, firmware, software, and platform teams.)
Then Education:Education (Minimum Qualifications): Bachelors in electrical, Computer Engineering, or related field. A master's degree is preferred.
Experience:Experience: 3+ years of experience in SoC power and performance validation. 3+ years of experience in Pre-Si simulation and emulation. 3+ years of experience developing and/or optimization of power/performance KPI's.
Technical Skills (2+ Years each): We could list as- .
Technical Skills (2+ Years of experience in each):
- with heading.
Preferred Qualifications: