Physical design Staff Application engineer

About the role

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. The Team You'll Be Part Of: Your recruiter will share more about the team structure and mission during the interview process.

Responsibilities

• Support customer engagements on advanced-node designs at 7nm, 5nm, and below using Synopsys physical design tools including Fusion Compiler, helping them hit PPA targets under real schedule and resource constraints
• Develop and enhance physical design methodologies and automation solutions using TCL, Python, and Perl to improve design quality, predictability, and team efficiency across the RTL-to-GDS flow
• Debug complex physical design challenges including placement, clock tree synthesis, routing, timing closure, and power optimization on FinFET designs with multi-patterning and electromigration constraints
• Build and deliver methodology recommendations tailored to customer design constraints, process technologies, and project timelines, not generic best practices but solutions that fit their specific context
• Contribute to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to solve implementation challenges that traditional methods struggle with
• Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature enhancements that make it into the next release
• Travel to customer sites as needed to provide onsite support, training, and design reviews, often under tight deadlines and high-stakes tape-out pressure

Requirements

• Bachelor's degree in electrical engineering or a related field with 5+ years of hands-on ASIC physical design experience, or a master's degree with 3+ years of experience
• Proficiency with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus, you have used these tools on real tapeouts, not just in training
• Strong scripting and automation skills using TCL, Python, or Perl to build flows, analyze data, and solve problems that do not have a button in the GUI
• Solid understanding of advanced-node design challenges at 7nm and below, including FinFET effects, multi-patterning, electromigration, and the tradeoffs that come with each
• Experience with logical and physical synthesis flows, and familiarity with AI-driven optimization methodologies is a strong plus
• Excellent communication and presentation skills, you can explain a complex timing closure strategy to a customer engineering team and a high-level roadblock to their management in the same meeting
• Willingness to travel to customer sites as needed, sometimes on short notice, to provide onsite support during critical design phases

Skills

• You can walk into a customer meeting with incomplete information, ask the right questions, and leave with a clear plan that the team actually believes in
• When a design is failing timing by 500ps and the customer is two weeks from tape-out, you do not panic, you methodically work the problem until you find the path to closure
• You write scripts that other engineers can actually read and modify, not just code that works but code that scales across a team
• You push back when a methodology recommendation does not fit the customer's reality, even if it means more work to find the right answer
• You can explain a complex physical design tradeoff to a VP in two sentences without losing the nuance, and then turn around and debug a TCL flow issue with an engineer
• You treat customer problems like your own, not because you have to but because you care about the outcome and you know your work directly affects whether their chip succeeds or fails

Benefits

We offer a comprehensive