Physical Design Intern

About The Role

Join our Physical Design team to help deliver next-generation SSD controller chips. As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL designs into functional physical layouts. You will gain hands-on experience in the complete ASIC flow from synthesis to tape-out, working on real projects in a fast-paced, innovative environment.

Responsibilities

• Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree synthesis (CTS), and routing.
• Perform static timing analysis (STA) and work to resolve setup and hold timing violations.
• Run and analyze design rule checks (DRC) and layout versus schematic (LVS) checks to ensure design integrity, as well as IR-Drop analysis.
• Assist in optimizing power, performance, and area (PPA) metrics using industry-standard EDA tools.
• Develop entire P&R/physical verification/IR-EM flows.
• Collaborate with front-end design and verification teams to seamlessly integrate RTL changes and resolve physical design constraints.
• Help generate and maintain physical design scripts, utilities, and documentation for the team.

Minimum Qualifications

• Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Foundational understanding of VLSI design concepts, CMOS circuit design, and digital logic.
• Familiarity with the basic stages of the ASIC physical design flow.
• Academic or project experience with scripting languages such as Python, Perl, or TCL.
• Strong analytical and problem-solving skills with a high attention to detail.

Preferred Qualifications

• Hands-on coursework or project experience with industry-standard EDA tools (e.g., Synopsys ICC2, Cadence Innovus, or similar).
• Exposure to Static Timing Analysis (STA) concepts and tools (e.g., PrimeTime, Tempus).
• Basic understanding of design constraints (SDC) and library exchange formats (LEF/DEF).
• Knowledge of low-power design techniques and power intent formats (UPF/CPF).
• Familiarity with AI/LLM tools (e.g., GPT, Copilot) and prompt engineering, with the ability to leverage them to automate EDA scripting, analyze design data, or optimize workflows.